Optimized Simulation Methodology of Warpage and Localized Stress Hotspot Prediction for Assembly Risk Assessment

• Main Authors: Yang, Zhi, Mellachervu, Krishna, Arsovski, Igor, Harames, Clint, Miller, Jim
• Format: Conference Proceeding
• Language: English
• Subjects: Accuracy; advanced packaging; Computational modeling; Costs; Data models; finite element analysis; integrated circuits; localized via stress modeling; Packaging; Predictive models; Stress; Warpage
• ISSN: 2377-5726
• DOI: 10.1109/ECTC51529.2024.00162

Generative Artificial Intelligence workloads, like Large Language Models, are growing in computational demand by 1000% every year, while Moore's Law scaling is only supplying 3% more transistors/mm2 every year. To close the gap between these wildly diverging demand and supply exponentials, the industry not only needs better chip-to-chip interconnects, but also ways to integrate more silicon into a single package. This paper we will focus on advanced packaging modeling of the Groq Language Processing Unit (LPU™) inference engine, the highest performance Large Language Model Inference Engine to date. More specifically the paper will focus on the accurate warpage prediction, which has emerged as a pivotal challenge with profound implications for design reliability and manufacturability.Accurate warpage/stress modeling techniques are essential to identify and visualize localized thermomechanical stress caused by coefficient of thermal expansion (CTE) mismatch between dissimilar materials within the board. As a result, failure prone and/ or high-risk regions are promptly revealed at an early design stage and mitigated through design optimization. However, the computational costs needed for such high-fidelity 3D simulation methodology are extremely expensive, time-consuming and almost impractical in real life. To resolve such accuracy-computational cost dilemma, this study investigates different modeling techniques to recommend an optimal balance between efficient simulation and accuracy.As the demand for higher performance of electronic devices with but lower power consumption requirement of electronic devices intensifies, smaller features, including finer line / space of copper traces, and higher aspect ratio vias between metal layers are becoming mainstream trends of today's board designs. However, this comes with even greater challenges of identifying the risk level for potential global warpage and localized fine features, such as traces and vias. Therefore, numerical finite element analysis (FEA) simulation plays an ever-increasing crucial role in the advanced packaging field, aiding in the reliability assessment and substrate / board risk mitigation during the assembly process.Simplest lumped method for warpage modeling is based on the rule-of-mixture theory that showed outlier warpage prediction against experimental measurement data. Recognizing the limitations of lumped modeling, industry has now started to adopt trace mapping techniques, which considers