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Novel three-layer stacking process with face-to-back CoW 6 μm-pitch hybrid bonding
We developed an innovative chip-on-wafer-on-wafer (CoWoW) process, involving a three-layer vertically stacked structure comprising face-to-back (F2B) chip-on-wafer (CoW) and face-to-face (F2F) wafer-on-wafer (WoW) using 6 μm-pitch Cu-Cu connections. We controlled the bowing of the top chip (17 × 24...
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creator | Urata, Akihiro Kamei, Takahiro Sakamoto, Akihisa Yoshioka, Hirotaka Hirano, Takaaki Shimizu, Kan Kagawa, Yoshihisa Iwamoto, Hayato |
description | We developed an innovative chip-on-wafer-on-wafer (CoWoW) process, involving a three-layer vertically stacked structure comprising face-to-back (F2B) chip-on-wafer (CoW) and face-to-face (F2F) wafer-on-wafer (WoW) using 6 μm-pitch Cu-Cu connections. We controlled the bowing of the top chip (17 × 24 mm, t = 0.15 mm) to achieve void-free CoW bonding. Moreover, we simulated the bonding strength of CoW using the elastic strain energy. Consequently, we obtained excellent 6 μm-pitch Cu-Cu connections of F2B CoW both at the center and the edge of the chip, as well as F2F WoW. Additionally, the 6 μm-pitch Cu-Cu connections using CoWoW exhibited high reliability in the stress-induced voiding and electromigration tests. These results demonstrated that a successful electrical connection through three layers could be achieved, proving that a process for three-layer stacked 3D heterogeneous integration could be established. |
doi_str_mv | 10.1109/ECTC51529.2024.00018 |
format | conference_proceeding |
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We controlled the bowing of the top chip (17 × 24 mm, t = 0.15 mm) to achieve void-free CoW bonding. Moreover, we simulated the bonding strength of CoW using the elastic strain energy. Consequently, we obtained excellent 6 μm-pitch Cu-Cu connections of F2B CoW both at the center and the edge of the chip, as well as F2F WoW. Additionally, the 6 μm-pitch Cu-Cu connections using CoWoW exhibited high reliability in the stress-induced voiding and electromigration tests. These results demonstrated that a successful electrical connection through three layers could be achieved, proving that a process for three-layer stacked 3D heterogeneous integration could be established.</description><identifier>EISSN: 2377-5726</identifier><identifier>EISBN: 9798350375985</identifier><identifier>DOI: 10.1109/ECTC51529.2024.00018</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>IEEE</publisher><subject>3D stacking ; Chip on Wafer (CoW) bonding ; Cows ; Cu-Cu hybrid bonding ; Electromigration ; Electronic components ; Face to Back ; Multichip modules ; Process control ; Stacking ; Three-dimensional displays</subject><ispartof>2024 IEEE 74th Electronic Components and Technology Conference (ECTC), 2024, p.56-61</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10565180$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,27904,54533,54910</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10565180$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Urata, Akihiro</creatorcontrib><creatorcontrib>Kamei, Takahiro</creatorcontrib><creatorcontrib>Sakamoto, Akihisa</creatorcontrib><creatorcontrib>Yoshioka, Hirotaka</creatorcontrib><creatorcontrib>Hirano, Takaaki</creatorcontrib><creatorcontrib>Shimizu, Kan</creatorcontrib><creatorcontrib>Kagawa, Yoshihisa</creatorcontrib><creatorcontrib>Iwamoto, Hayato</creatorcontrib><title>Novel three-layer stacking process with face-to-back CoW 6 μm-pitch hybrid bonding</title><title>2024 IEEE 74th Electronic Components and Technology Conference (ECTC)</title><addtitle>ECTC</addtitle><description>We developed an innovative chip-on-wafer-on-wafer (CoWoW) process, involving a three-layer vertically stacked structure comprising face-to-back (F2B) chip-on-wafer (CoW) and face-to-face (F2F) wafer-on-wafer (WoW) using 6 μm-pitch Cu-Cu connections. We controlled the bowing of the top chip (17 × 24 mm, t = 0.15 mm) to achieve void-free CoW bonding. Moreover, we simulated the bonding strength of CoW using the elastic strain energy. Consequently, we obtained excellent 6 μm-pitch Cu-Cu connections of F2B CoW both at the center and the edge of the chip, as well as F2F WoW. Additionally, the 6 μm-pitch Cu-Cu connections using CoWoW exhibited high reliability in the stress-induced voiding and electromigration tests. These results demonstrated that a successful electrical connection through three layers could be achieved, proving that a process for three-layer stacked 3D heterogeneous integration could be established.</description><subject>3D stacking</subject><subject>Chip on Wafer (CoW) bonding</subject><subject>Cows</subject><subject>Cu-Cu hybrid bonding</subject><subject>Electromigration</subject><subject>Electronic components</subject><subject>Face to Back</subject><subject>Multichip modules</subject><subject>Process control</subject><subject>Stacking</subject><subject>Three-dimensional displays</subject><issn>2377-5726</issn><isbn>9798350375985</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2024</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotjEtOwzAURQ0SEqV0Bx14Ay5-dvwboqh8pAoGFDGsHPuFGNImiiNQ9sYaWBNFMLqDc84lZAl8BcDd1brclgqUcCvBRbHinIM9IQtnnJWKS6OcVadkJqQxTBmhz8lFzm-cF7_ijDw9dB_Y0rEZEFnrJxxoHn14T4dX2g9dwJzpZxobWvuAbOxYdYS07F6opt9fe9anMTS0maohRVp1h3gML8lZ7duMi_-dk-eb9ba8Y5vH2_vyesMSyGJkEWsXHQBG6Sx4rb11CgpZaeGiAPSm8BF8MNYV2kvQIToluLdglRZByTlZ_v0mRNz1Q9r7YdoBV1qB5fIHdudQsQ</recordid><startdate>20240528</startdate><enddate>20240528</enddate><creator>Urata, Akihiro</creator><creator>Kamei, Takahiro</creator><creator>Sakamoto, Akihisa</creator><creator>Yoshioka, Hirotaka</creator><creator>Hirano, Takaaki</creator><creator>Shimizu, Kan</creator><creator>Kagawa, Yoshihisa</creator><creator>Iwamoto, Hayato</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20240528</creationdate><title>Novel three-layer stacking process with face-to-back CoW 6 μm-pitch hybrid bonding</title><author>Urata, Akihiro ; Kamei, Takahiro ; Sakamoto, Akihisa ; Yoshioka, Hirotaka ; Hirano, Takaaki ; Shimizu, Kan ; Kagawa, Yoshihisa ; Iwamoto, Hayato</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i134t-def9d911ed3981a66a895143b629d21ea74ad1ac78946a316cd9520a818562c53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2024</creationdate><topic>3D stacking</topic><topic>Chip on Wafer (CoW) bonding</topic><topic>Cows</topic><topic>Cu-Cu hybrid bonding</topic><topic>Electromigration</topic><topic>Electronic components</topic><topic>Face to Back</topic><topic>Multichip modules</topic><topic>Process control</topic><topic>Stacking</topic><topic>Three-dimensional displays</topic><toplevel>online_resources</toplevel><creatorcontrib>Urata, Akihiro</creatorcontrib><creatorcontrib>Kamei, Takahiro</creatorcontrib><creatorcontrib>Sakamoto, Akihisa</creatorcontrib><creatorcontrib>Yoshioka, Hirotaka</creatorcontrib><creatorcontrib>Hirano, Takaaki</creatorcontrib><creatorcontrib>Shimizu, Kan</creatorcontrib><creatorcontrib>Kagawa, Yoshihisa</creatorcontrib><creatorcontrib>Iwamoto, Hayato</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Urata, Akihiro</au><au>Kamei, Takahiro</au><au>Sakamoto, Akihisa</au><au>Yoshioka, Hirotaka</au><au>Hirano, Takaaki</au><au>Shimizu, Kan</au><au>Kagawa, Yoshihisa</au><au>Iwamoto, Hayato</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Novel three-layer stacking process with face-to-back CoW 6 μm-pitch hybrid bonding</atitle><btitle>2024 IEEE 74th Electronic Components and Technology Conference (ECTC)</btitle><stitle>ECTC</stitle><date>2024-05-28</date><risdate>2024</risdate><spage>56</spage><epage>61</epage><pages>56-61</pages><eissn>2377-5726</eissn><eisbn>9798350375985</eisbn><coden>IEEPAD</coden><abstract>We developed an innovative chip-on-wafer-on-wafer (CoWoW) process, involving a three-layer vertically stacked structure comprising face-to-back (F2B) chip-on-wafer (CoW) and face-to-face (F2F) wafer-on-wafer (WoW) using 6 μm-pitch Cu-Cu connections. We controlled the bowing of the top chip (17 × 24 mm, t = 0.15 mm) to achieve void-free CoW bonding. Moreover, we simulated the bonding strength of CoW using the elastic strain energy. Consequently, we obtained excellent 6 μm-pitch Cu-Cu connections of F2B CoW both at the center and the edge of the chip, as well as F2F WoW. Additionally, the 6 μm-pitch Cu-Cu connections using CoWoW exhibited high reliability in the stress-induced voiding and electromigration tests. These results demonstrated that a successful electrical connection through three layers could be achieved, proving that a process for three-layer stacked 3D heterogeneous integration could be established.</abstract><pub>IEEE</pub><doi>10.1109/ECTC51529.2024.00018</doi><tpages>6</tpages></addata></record> |
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issn | 2377-5726 |
language | eng |
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source | IEEE Xplore All Conference Series |
subjects | 3D stacking Chip on Wafer (CoW) bonding Cows Cu-Cu hybrid bonding Electromigration Electronic components Face to Back Multichip modules Process control Stacking Three-dimensional displays |
title | Novel three-layer stacking process with face-to-back CoW 6 μm-pitch hybrid bonding |
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