Gate Oxide Failure Mechanisms of SiC MOSFET Related to Electro-Thermomechanical Stress Under HTRB and HTGB Test

• Main Authors: Ren, Min, Liang, Shiqi, Zhou, Tong, Gu, Hang, Gao, Wei, Pi, Meng, Tang, Yuting, Liu, Zhihai, Li, Zehong, Guo, Xinkai, Dai, Maozhou, Zhang, Bo
• Format: Conference Proceeding
• Language: English
• Subjects: component; formatting; insert; Layout; Logic gates; MOSFET; Reliability; Silicon; Silicon carbide; style; styling; Thermomechanical processes
• ISSN: 1946-0201
• DOI: 10.1109/ISPSD59661.2024.10579620

Reliability issues with the gate oxide remain a significant obstacle to the widespread application of SiC MOSFET devices. This work reveals the gate oxide failure of SiC MOSFETs not only related to gate oxide defects and high electric fields but also to thermomechanical stress. During the High Temperature Reverse Bias (HTRB) and High Temperature Gate Bias (HTGB) tests, the unique structure of the MOSFET device cells and gate pad transition region experiences concentrated thermomechanical stress at high temperatures, as the mismatch in coefficient of thermal expansion (CTE) between SiC/SiO 2 and Poly-Si/SiC leads to more pronounced stress concentration, resulting in gate oxide failure in these areas. In the HTGB test, the high electric field in the gate oxide accelerates the failure process in conjunction with thermomechanical stress. By optimizing the layout pattern and process, the mechanical stress at the failure point was reduced by 56.5%, and the optimized devices passed 1000 hours of HTRB and HTGB testing.