Design Space Exploration of FFT Accelerators for IEEE 802.11ax using High-Level Synthesis

Fast Fourier transform (FFT) accelerators for IEEE 802.11ax (WiFi 6) must be designed to satisfy the stringent performance requirements specified by the standard. The design space consisting of several architectural options such as radix, memory port and loop/block pipelining is explored to optimize...

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Bibliographic Details
Main Authors: Lee, Uyong, Park, Yeji, Heo, Junsu, Park, Sungkyung, Park, Chester Sungchung
Format: Conference Proceeding
Language:English
Subjects:
DSE
Fast Fourier transforms
FFT
HLS
IEEE 802.11ax
IEEE 802.11ax Standard
Iterative decoding
pipelining
Receivers
Space exploration
Systems architecture
Throughput
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Summary:Fast Fourier transform (FFT) accelerators for IEEE 802.11ax (WiFi 6) must be designed to satisfy the stringent performance requirements specified by the standard. The design space consisting of several architectural options such as radix, memory port and loop/block pipelining is explored to optimize an FFT accelerator. Moreover, the relevant ablation study is conducted to evaluate the impact of each architectural option on the area and performance of an FFT accelerator. A commercially available high-level synthesis (HLS) tool is used to efficiently perform the design space exploration (DSE). The experimental results show that a radix-4, dual-port, fully-pipelined FFT accelerator decreases the latency by 4.7x and increases the throughput by 3x, compared to the baseline, thereby satisfying the system requirements for iterative detection and decoding (IDD) for IEEE 802.11ax. It is also shown that the proposed DSE using HLS helps to achieve a 5% improvement in area-delay product (ADP) while consuming significantly less design time than the conventional hand-coded RTL designs.
ISSN:2160-052X
DOI:10.1109/ASAP61560.2024.00033