A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications

Frequent data conversion in analog compute-in-memory (ACiM) reduces the benefits obtained by analog computing. This paper proposes an efficient signed 8b multiple-accumulate (MAC) unit with hybrid differential capacitor ladders. Then a sparsity-aware DAC and an embedded SAR-ADC are introduced to low...

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Bibliographic Details
Main Authors: Wang, Hechen, Liu, Renzhi, Dorrance, Richard, Dasalukunte, Deepak, Gowda, Niranjan, Carlton, Brent
Format: Conference Proceeding
Language:English
Subjects:
Artificial intelligence
Capacitors
Data conversion
In-memory computing
Very large scale integration
Online Access:Request full text
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Summary:Frequent data conversion in analog compute-in-memory (ACiM) reduces the benefits obtained by analog computing. This paper proposes an efficient signed 8b multiple-accumulate (MAC) unit with hybrid differential capacitor ladders. Then a sparsity-aware DAC and an embedded SAR-ADC are introduced to lower the data conversion overhead. Finally, two activation functions (AFs) are included to further improve efficiency: 1) ReLU is realized by SAR-ADC LSB skipping; 2) tanh is built with analog buffers to bypass data converters.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631356