A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications

This work presents an energy-efficient CIM-CAM processor for both neural network (NN) and recommendation system (RecSys) applications. The main contributions include: 1) A reconfigurable Zig-Zag memory access architecture for diverse convolution/MVM to minimize SRAM access; 2) A backbone-systolic CI...

Full description

Saved in:
Bibliographic Details
Main Authors: Dai, Zhuoyu, Yan, Shengzhe, Cong, Zhaori, Guo, Zeyu, He, Yifan, Sun, Wenyu, Dou, Chunmeng, Zhang, Feng, Yue, Jinshan, Liu, Yongpan, Liu, Ming
Format: Conference Proceeding
Language:English
Subjects:
Artificial neural networks
Common Information Model (computing)
Energy efficiency
In-memory computing
Memory architecture
Random access memory
Very large scale integration
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This work presents an energy-efficient CIM-CAM processor for both neural network (NN) and recommendation system (RecSys) applications. The main contributions include: 1) A reconfigurable Zig-Zag memory access architecture for diverse convolution/MVM to minimize SRAM access; 2) A backbone-systolic CIM array towards a higher system/macro efficiency ratio; 3) A distribution-aware block/self-gating (DABG) CAM to reduce both off-chip access and on-chip search power for the memory-dominate embedding layer. The fabricated 28nm chip demonstrates 37.9-81.5TOPS/W system energy efficiency for NN and 12.3-56.1nJ/request for RecSys. This work achieves 2.4\times/3.6\times energy/area efficiency for NN and 370\times energy reduction for RecSys compared with the state-of-the-art.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631368