First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s)

This work firstly demonstrates a monolithic 3D architecture with ultra-high density IGZO/Si SRAM and IGZO 2T0C DRAM (M3D-SD) integrated in 3-tiers. By incorporating ultra-low leakage IGZO transistor in tier 2 as pass gate and BEOL integration on Si-CMOS cross-coupled inverters (Tier 1), a hybrid IGZ...

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Bibliographic Details
Main Authors: Liu, Menggan, Li, Zhi, Lu, Wendong, Chen, Kaifei, Niu, Jiebin, Liao, Fuxi, Wu, Zijing, Lu, Congyan, Li, Wei zeng, Geng, Di, Lu, Nianduan, Dou, Chunmeng, Yang, Guanhua, Li, Ling, Liu, Ming
Format: Conference Proceeding
Language:English
Subjects:
Data transfer
Hybrid power systems
Inverters
Logic gates
Random access memory
Three-dimensional displays
Very large scale integration
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Summary:This work firstly demonstrates a monolithic 3D architecture with ultra-high density IGZO/Si SRAM and IGZO 2T0C DRAM (M3D-SD) integrated in 3-tiers. By incorporating ultra-low leakage IGZO transistor in tier 2 as pass gate and BEOL integration on Si-CMOS cross-coupled inverters (Tier 1), a hybrid IGZO/Si SRAM is demonstrated with ultra-high density of 4T footprint and 51% reduced static power. In addition, IGZO 2T0C DRAM is integrated in tier 3, which achieves SRAM-DRAM data transfer with record-low latency (
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631551