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First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s)
This work firstly demonstrates a monolithic 3D architecture with ultra-high density IGZO/Si SRAM and IGZO 2T0C DRAM (M3D-SD) integrated in 3-tiers. By incorporating ultra-low leakage IGZO transistor in tier 2 as pass gate and BEOL integration on Si-CMOS cross-coupled inverters (Tier 1), a hybrid IGZ...
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| creator | Liu, Menggan Li, Zhi Lu, Wendong Chen, Kaifei Niu, Jiebin Liao, Fuxi Wu, Zijing Lu, Congyan Li, Wei zeng Geng, Di Lu, Nianduan Dou, Chunmeng Yang, Guanhua Li, Ling Liu, Ming |
| description | This work firstly demonstrates a monolithic 3D architecture with ultra-high density IGZO/Si SRAM and IGZO 2T0C DRAM (M3D-SD) integrated in 3-tiers. By incorporating ultra-low leakage IGZO transistor in tier 2 as pass gate and BEOL integration on Si-CMOS cross-coupled inverters (Tier 1), a hybrid IGZO/Si SRAM is demonstrated with ultra-high density of 4T footprint and 51% reduced static power. In addition, IGZO 2T0C DRAM is integrated in tier 3, which achieves SRAM-DRAM data transfer with record-low latency ( |
| doi_str_mv | 10.1109/VLSITechnologyandCir46783.2024.10631551 |
| format | conference_proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | EISSN: 2158-9682 |
| ispartof | 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2 |
| issn | 2158-9682 |
| language | eng |
| recordid | cdi_ieee_primary_10631551 |
| source | IEEE Xplore All Conference Series |
| subjects | Data transfer Hybrid power systems Inverters Logic gates Random access memory Three-dimensional displays Very large scale integration |
| title | First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s) |
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