An 80-NS NDRO ferrite core memory design

The use of fast-rising short-duration pulses in the design of a 1K - 144 bit NDRO memory with permeability sensing leads to high-frequency considerations not normally encountered in ferrite core memories. In particular, the high-frequency character of the device must be recognized to properly evalua...

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Bibliographic Details
Published in:IEEE transactions on magnetics 1967-09, Vol.3 (3), p.316-320
Main Authors: Bosch, L., Flaker, R., Hottenrott, H., Lockhart, N.
Format: Article
Language:English
Subjects:
Character recognition
Circuits
Computational geometry
Control systems
Electric variables control
Ferrites
Permeability
System testing
Writing
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Summary:The use of fast-rising short-duration pulses in the design of a 1K - 144 bit NDRO memory with permeability sensing leads to high-frequency considerations not normally encountered in ferrite core memories. In particular, the high-frequency character of the device must be recognized to properly evaluate cycle time capabilities and array transmission. The design of this memory centers around a 2-core-per-bit word-organized array. The array was optimized with the aid of a computer analysis that considered the device, array geometry, and line termination as variables. The performance of this system has been tested by a cross-section model incorporating full length, fully populated word and digit lines.
ISSN:0018-9464
1941-0069
DOI:10.1109/TMAG.1967.1066136