Design and Performance Evaluation of an Adaptive Routing Algorithm for RISC-V Based NoC Architecture

• Main Authors: Kumar Reddy, B. Naresh, Sai Kumar, Aruru, Krishna, Y. Charan
• Format: Conference Proceeding
• Language: English
• Subjects: Adaptive Router; Adaptive systems; Computer architecture; FGPA; Heuristic algorithms; Multiprocessor System-on-Chip; Network Interface; Network-on-Chip; RISC-V; Routing; Switches; Topology; Wireless communication
• ISSN: 2766-2101
• DOI: 10.1109/CONECCT62155.2024.10677242

Due to the increasing complexity of modern System-on-Chip (SoC) designs, classical and multi-layer bus architectures are inadequate for meeting the needs of inter-core communication. High-performance, low-power chips for a wide variety of uses, including wireless communication and multimedia processing, will benefit greatly from NoC technology. The current RISC-V architecture is based on the open ISA standard, which is seeing rapid adoption. Using oblivious permutation routing, the Network Interface (NI) architecture may port a 32-bit RISC-V core to the on-chip communication infrastructure utilized by the MPSoC. In this work, we proposed a dynamic adaptive routing algorithm that involves routers for exchanging and updating router table data, to follow changes in the traffic and topology. The main goals of adaptive routing are to help prevent packet delivery failure, enhance encryption for network efficiency, and lifetime reliability, and aid in controlling network congestion. The proposed architecture will be synthesized and simulated using Vivado Design Suite 2023.1 and realized on a Zynq 7000 SoC ZC706 Evaluation Kit.