Energy-Efficient Power Analysis Attack Resilient Adiabatic MTJ-Based Nonvolatile CLB

• Main Authors: Nasab, Milad Tanavardi, Yang, Wu, Thapliyal, Himanshu
• Format: Conference Proceeding
• Language: English
• Subjects: Adiabatic Secure FPGA; Configurable Logic Block; Energy consumption; Energy efficiency; Magnetic Tunnel Junction; Measurement; Power Analysis Attack; Power supplies; Side-channel attacks; Simulation; Spintronic; Very large scale integration
• ISSN: 2159-3477
• DOI: 10.1109/ISVLSI61997.2024.00090

Energy efficiency and security against side-channel attacks (like power analysis attacks) in modern and battery-operated applications like IoT and medical applications are vital. On the other hand, FPGAs are widely used as a hardware platform for these applications. Accordingly, energy-efficient and power analysis attack-resilient design for FPGA is required. This paper proposes an energy-efficient power analysis attack-resilient adiabatic nonvolatile hybrid MTJ/CMOS LiM-based CLB. The simulation results show that the proposed design has 98.72%, 98.72%, 98.69%, 98.61 %, 98.43%, and 98.11 % (at least 84.69%, 84.74%, 84.28%, 83.19%, 80.70%, and 77%) lower energy consumption compared to its CMOS counterpart (adiabatic counterparts) for frequencies of 1, 2.5, 5, 10, 20, and 40 MHz, respectively. Also, the proposed design keeps its energy consumption superiority for different TMR and power supply voltages, compared to its counterparts. The NED and NSD values of different designs have been calculated and used as power analysis attack-resiliency metrics. The results show that the proposed design has 1053x and 1628x (at least 23x and 14x) lower NED and NSD values compared to its CMOS counterpart (adiabatic counterparts). Furthermore, the NED and NSD values of the proposed design stay in the same range (10 −4 ) for different frequencies, power supply voltages, and TMR.