A new high-performance programmable delay line IC

A novel implementation of a programmable digital delay line based on a shift register for video applications is presented. An optimized register developed to reduce the power dissipation of the register files is described. A compromise between the power dissipation and area of the circuit is used to...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on consumer electronics 1989-11, Vol.35 (4), p.893-900
Main Authors: Dejhan, K., Jutand, F., Demassieux, N., Colavin, O., Galisson, A., Artieri, A.
Format: Article
Language:English
Subjects:
Applied sciences
Circuits
CMOS technology
Delay lines
Electric, optical and optoelectronic circuits
Electronics
Exact sciences and technology
Filters
Frequency
Image converters
Pixel
Power dissipation
Random access memory
Shift registers
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A novel implementation of a programmable digital delay line based on a shift register for video applications is presented. An optimized register developed to reduce the power dissipation of the register files is described. A compromise between the power dissipation and area of the circuit is used to obtain high performance. The chip features a 20-MHz operating frequency and 200-mW power dissipation. This chip has been designed with a 1.2- mu m CMOS technology.< >
ISSN:0098-3063
1558-4127
DOI:10.1109/30.106914