A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS

• Published in: IEEE journal of solid-state circuits 2024-09, p.1-14
• Main Authors: Park, Sungjin, Lee, Sunwoo, Park, Jeongwoo, Choi, Hyeong-Seok, Lee, Kyogu, Jeon, Dongsuk
• Format: Article
• Language: English
• Subjects: Computational modeling; Convolution; Decoding; Digital hearing aids; Hearing aids; multiplier-less processing element (PE); neural network processor; Neural networks; Optimization; Real-time systems; reconfigurable architecture; speech enhancement (SE)
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2024.3460426

Speech enhancement (SE) plays a key role in many audio-related applications by removing noise and enhancing the quality of human voice. Recent deep learning-based approaches provide high-quality SE, but real-time processing of those algorithms is challenging in resource-constrained devices due to high computational complexity. In this article, we present an energy-efficient real-time SE processor aimed at hearing aids. To implement high-quality SE with a very limited power budget, various algorithm and hardware optimization techniques are proposed. Our SE algorithm adaptively allocates computational resources to each region in the input feature domain depending on their importance, reducing overall computations by 29.7%. Along with 4-bit channel-wise logarithmic quantization, the processor adopts a reconfigurable multiplier-less processing element (PE) that supports both pre-/post-processing and neural network layers, resulting in a 21.5% area reduction. In addition, the design employs efficient scheduling and input buffering schemes to reduce on-chip memory access by 70.8%. Fabricated in a 28-nm CMOS process, our design consumes only 740 \mu W at 2.5 MHz with a total latency of 39.96 ms, satisfying the real-time processing constraints. In addition, our approach demonstrated higher SE quality than prior art in both objective and subjective evaluations.