E3HDC: Energy Efficient Encoding for Hyper-Dimensional Computing on Edge Devices

Hyper-Dimensional Computing (HDC) as a brain-inspired computational model for cognitive tasks is suitable for edge devices due to its hardware-friendly and fault-resistant computations. Despite this potential, HDC has a large memory footprint, resulting high power consumption. In this work, we propo...

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Bibliographic Details
Main Authors: Roodsari, Mahboobe Sadeghipour, Krautter, Jonas, Meyers, Vincent, Tahoori, Mehdi
Format: Conference Proceeding
Language:English
Subjects:
Accuracy
Computational modeling
configurable design
edge device
Encoding
Energy efficiency
Field programmable gate arrays
Hardware
HDC
hyperdimensional computing
Internet of Things
IoT
Logic
low power
Memory management
Power demand
Training
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Description
Summary:Hyper-Dimensional Computing (HDC) as a brain-inspired computational model for cognitive tasks is suitable for edge devices due to its hardware-friendly and fault-resistant computations. Despite this potential, HDC has a large memory footprint, resulting high power consumption. In this work, we propose a hardware-aware encoding where parameters are generated on-the-fly without any large memory block requirements. Moreover, the hardware mapping of the trained HDC model is optimized to make it suitable for resource-constraint edge devices. In this work we propose an end-to-end flow from HDC training to FPGA mapping. We demonstrate the efficiency of this method compared to other state-of-the-art HDC implementations in terms of hardware usage and power consumption.
ISSN:1946-1488
DOI:10.1109/FPL64840.2024.00045