Rapid On-Wafer Quality Screening of AlGaN/GaN Superlattice Castellated Field Effect Transistors Using Short-Term Stress and Electroluminescence

• Published in: IEEE electron device letters 2024-01, Vol.45 (12), p.2503-2505
• Main Authors: Parvez, Bazila, Kumar, Akhil S., Pomeroy, James W., Smith, Matthew D., Howell, Robert S., Kuball, Martin
• Format: Article
• Language: English
• Subjects: Aluminum gallium nitride; Aluminum gallium nitrides; Breakdown voltage (BV); Current leakage; Damage assessment; Degradation; Dielectrics; Electric potential; Electroluminescence; electroluminescence (EL); Field effect transistors; Gallium nitrides; HEMTs; hot electrons; Leakage current; Logic gates; MODFETs; Screening; Semiconductor devices; step-stress; Stress; Stress measurement; super-lattice castellated field effect transistors (SLCFETs); Superlattices; Transistors; Voltage; Voltage measurement; Wide band gap semiconductors
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2024.3478073

A electroluminescence (EL) based methodology has been devised to screen AlGaN/GaN Super-Lattice Castellated Field Effect Transistors (SLCFETs). EL intensity captured during off-state stressing has been correlated with an increase in gate leakage current after stress. Two off-state constant-voltage stress conditions were used, both applied over a stress time ( {\mathrm {t}}_{\text {stress}} ) of 90 seconds: (a) {\mathrm{V}}_{\text {GS}} = -12 V, {\mathrm{V}}_{\text {DS}} = 12 V, and (b) {\mathrm{V}}_{\text {GS}} = -12 V, {\mathrm{V}}_{\text {DS}} = 14 V. The integrated EL intensity was found to scale with the ratio of off-state gate leakage current before and after the stress. The results were verified using step-stress tests to find the breakdown voltage (BV) of the gate dielectric of the stressed devices. BV was again found to scale with the measured integrated EL intensity for both the stress conditions. The results show that a short duration off-state stress in conjunction with EL can be a beneficial tool for quick assessment of the quality of gate dielectric across the wafer without incurring any significant damage to the devices. This becomes especially useful for rapid on-wafer device screening during large-scale production.