A 5.3-μW 80.8-dB SNDR LNA-Embedded EF-CIFF Third-Order Noise-Shaping SAR ADC for Closed-Loop Neural Recording

• Main Authors: Kim, Yegeun, Seok, Changhun, Jeong, Kyeongwon, Choi, Haidam, Choee, Heewon, Ha, Sohmyung, Je, Minkyu
• Format: Conference Proceeding
• Language: English
• Subjects: amplifier-embedded; closed-loop neural recording; CMOS process; Europe; Feedforward neural networks; In vitro; Low-noise amplifiers; Noise shaping; Power demand; Recording; Registers; Signal to noise ratio; successive approximation register (SAR)
• ISSN: 2643-1319
• DOI: 10.1109/ESSERC62670.2024.10719405

This work presents a 3rd-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) employing an error feedback-cascaded integrator feedforward (EF-CIFF) structure where a low-noise amplifier (LNA) is embedded, which operates for neural recording at a low oversampling ratio (OSR). By employing the 3rd-order EFCIFF NS-SAR ADC and embedded low-gain LNA, it achieves low input-referred noise (IRN) while offering a sufficiently wide input range so that stimulation artifacts can be accommodated when applied to closed-loop neural interface systems. By reusing the LNA, it can implement PVT-robust charge summation with good driving ability in the error feedback (EF) path without consuming additional power. Fabricated in a 180-\mathrm{nm} CMOS process, the proposed IC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 80.8 dB with an OSR of 16 and a 2.5 kHz signal bandwidth (BW), while consuming 5.3 \mu \mathrm{~W} from a 1.2-\mathrm{V} supply. This results in a Schreier's figure of merit (FOM) of 167.5 dB.