A 18 nm FD-SOI CMOS 6.38 mW 15 fps 8 -bit features 14.8 μJ/inference QVGA road-traffic monitoring Edge AI SoC demonstrator

• Main Authors: Clerc, Sylvain, Taly, Emilien, Heinrich, Vincent, Bain, Nathan, Oudrhiri, Ali, Krauth, Lucille, Blampey, Alexandre, Blanc, Christophe Le, Bernabovi, Stefano, Lafage, Anne, Benalla, Anas, Paille, Bruno, Potot, Jerome, Gueze, Didier, Riquet, Damien, Marchal, Sebastien, Bousquet, Dominique, Gras, Raphael, Lacouture, Stephane, Guizzetti, Roberto, Mangano, Christophe-Victor, Lecocq, Christophe, Hulot, Stephane, Djouder, Mourad, Biard, Sylvain, Weber, Olivier, Wilson, Robin, Nimsgern, Fabien, Cathelin, Andreia, Arnaud, Franck, Urard, Pascal
• Format: Conference Proceeding
• Language: English
• Subjects: Edge AI; Europe; Monitoring; Process control; Road traffic; Roads; Single instruction multiple data; Temperature measurement; Temperature sensors; Tensors
• ISSN: 2643-1319
• DOI: 10.1109/ESSERC62670.2024.10719433

This paper presents an autonomous road traffic monitoring Edge AI SoC implemented in 18nm FD-SOI CMOS. The SoC includes a RISC-V CPU, a 128 Processing Elements (PE) Single Instruction Multiple Data (SIMD) Tensor Processing Unit (TPU) AI accelerator, with QVGA and control interfaces. It uses Adaptative-Body-Bias (ABB) process and temperature compensation. The circuit operates within 0.5 to 0.87 \mathrm{~V},-40 to 140^{\circ} \mathrm{C}, 50 to 500 MHz ranges. The TPU efficiency energy per inference and latency are 3.52 \mu \mathrm{~J} and 0.616 ms when running MobileNet v1 stripped by 2 layers, and 14.8 \mu \mathrm{~J} and 2.27 ms when running traffic monitoring application. For this latter application, the circuit total power is 6.38 mW at 15 fps 0.5 V supply.