A 1095 pJ/b 219 Mb/s Application-specific Instruction-set Processor for Distributed Massive MIMO in 22FDX

Distributed massive multiple-input multiple-output (D-MIMO) has been identified as a promising technology to meet the service requirements of 6 G wireless networks and beyond. The coordination between a massive number of distributed antennas introduces stiff challenges and requires a substantial amo...

Full description

Saved in:
Bibliographic Details
Main Authors: Attari, Mohammad, Sanchez, Jesus Rodriguez, Edfors, Ove, Liu, Liang
Format: Conference Proceeding
Language:English
Subjects:
baseband ASIP
Distributed massive MIMO
Energy efficiency
Europe
Golub-Kahan
Hardware acceleration
Instruction sets
Massive MIMO
matrix decomposition
Memory management
Power demand
RISC-V
SIMD
Single instruction multiple data
SVD accelerator
systolic array
Vectors
Wireless networks
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Distributed massive multiple-input multiple-output (D-MIMO) has been identified as a promising technology to meet the service requirements of 6 G wireless networks and beyond. The coordination between a massive number of distributed antennas introduces stiff challenges and requires a substantial amount of computing resources that must be put together with careful algorithm-architecture codesign. The process places a premium on flexibility, and toward this end the current paper presents an application-specific instruction set processor (ASIP) utilizing single instruction multiple data (SIMD), allied with programmer-visible hardware accelerators and a specialized memory subsystem, and employed in distributed and scalable massive MIMO systems. The chip is fabricated using the GF22nm FDX technology.
ISSN:2643-1319
DOI:10.1109/ESSERC62670.2024.10719451