A Compact 21-25 GHz Charge-Domain Fractional-N ADPLL with 168 fs Total RMS Jitter

We propose a fractional-N ADPLL featuring a phase detector (PD) operating in charge-domain by charge-steering sampling of a sinusoidal reference waveform. The periodic fractional-N phase error pattern is compensated by an implicit C-DAC taking on the conventional role of a digital-to-time converter....

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Bibliographic Details
Main Authors: Tao, Weichen, Liu, Yongheng, Yang, Yuhao, Staszewski, R. Bogdan, Lin, Fujiang, Hu, Yizhe
Format: Conference Proceeding
Language:English
Subjects:
ADPLL
Charge-steering sampling (CSS)
Detectors
Europe
fractional-N
Jitter
low-jitter
mm-wave
Phase detection
phase detector (PD)
Phase locked loops
Power demand
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Description
Summary:We propose a fractional-N ADPLL featuring a phase detector (PD) operating in charge-domain by charge-steering sampling of a sinusoidal reference waveform. The periodic fractional-N phase error pattern is compensated by an implicit C-DAC taking on the conventional role of a digital-to-time converter. By re-interpreting the multi-bit PD output as mid-rise encoded, its gain is boosted by bang-bang effects, thus mitigating the slow slope of reference waveform, while avoiding the disadvantages of prior-art bang-bang PDs. Total rms jitter is 96 \mathrm{fs}-\mathrm{rms} at 24 GHz with reference spurs of −60 dBc in integer-N, while 168 fs with worst in-band spurs of −46 dBc in a fractional-N mode. The occupied area is only 0.08 \mathrm{~mm}^{2}.
ISSN:2643-1319
DOI:10.1109/ESSERC62670.2024.10719460