A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage

This paper presents NMOS header assist cell (NHAC) that lowers SRAM VMin with minimal power overhead for low power applications. The proposed NHAC, featuring a bitcell-compatible layout, is inserted between cell arrays to provide cell power. NHAC achieves a VMIN improvement of 210 mV with 4% power o...

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Bibliographic Details
Main Authors: Kang, Jungmyung, Cho, Keonhee, Kim, Sekeon, Kim, Giseok, Kim, Hyunjun, Seo, Dongwook, Baeck, Sangyeop, Yoon, Seiseung, Jung, Seong-Ook
Format: Conference Proceeding
Language:English
Subjects:
assist cell
Clamps
Costs
Electrical resistance measurement
Europe
Integrated circuit interconnections
interconnect resistance
Layout
MOS devices
nmos header
Random access memory
Resistance
retention leakage
self-collapse
Semiconductor device measurement
Static random access memory (SRAM)
write assist circuit
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Summary:This paper presents NMOS header assist cell (NHAC) that lowers SRAM VMin with minimal power overhead for low power applications. The proposed NHAC, featuring a bitcell-compatible layout, is inserted between cell arrays to provide cell power. NHAC achieves a VMIN improvement of 210 mV with 4% power overhead, even in the high interconnect resistance case, thanks to the continuous self-collapse of cell power voltage. Additionally, enabling all NHACs in sleep mode reduces bitcell retention leakage by 25% to 61% without additional area cost.
ISSN:2643-1319
DOI:10.1109/ESSERC62670.2024.10719479