A 112-Gb/s PAM-4 Receiver with Ultra-Fine GainAdjustment CTLE and Novel Sample-and-Reset Slicer in 28-nm CMOS

• Main Authors: Tang, Renjie, Wang, Ka'Nan, Sun, Huanfa, Cao, Chenyao, Wei, Shangjie, Su, Yu, He, Yukun, Chen, Xi'An, Yang, Haidong, Lin, Shengzhang, Xiao, Yang, Li, Min, Wang, Lei, Gui, Xiaoyan
• Format: Conference Proceeding
• Language: English
• Subjects: clock and data recovery; Clocks; continuous-time linear equalizer; Detectors; Energy efficiency; Equalizers; Europe; Frequency measurement; Interference; Loss measurement; PAM-4; Receiver; Receivers; sample-and-reset slicer; Signal resolution
• ISSN: 2643-1319
• DOI: 10.1109/ESSERC62670.2024.10719519

A 112-Gb/s mixed-signal 4-level pulse amplitude modulation (PAM-4) receiver (RX) with clock-data recovery (CDR) for extra-short-reach (XSR) applications is presented. An ultra-fine gain-adjustment continuous-time linear equalizer (CTLE) is introduced to deal with the channel loss as well as the long-term inter-symbol interference (ISI). A novel quarter-rate multi-stage slicer with eight-phase clocking and rapid reset in the phase detectors (PDs) is proposed, which is capable of resolving 112-Gb/s PAM-4 signal in 28-\mathrm{nm} CMOS. A Bang-Bang CDR with programmable bandwidth followed by a 7-bit phase interpolator recovers the 14-\mathrm{GHz} 1 / 4-rate clock. The PAM-4 receiver fabricated in 28-\mathrm{nm} CMOS achieves bit-error-rate (BER) better than 1E-12 with PRBS-7 measured over a channel with 12dB loss at Nyquist frequency. Attributed to first-time implementation of 1 / 4-rate 112-Gb/s PAM-4 receiver in 28-\mathrm{nm} CMOS, this work achieves the best energy efficiency of 0.97 \mathrm{pJ} / bit among other PAM-4 receivers at similar process nodes.