A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs

This work presents a 48-58GHz DTC based FracN DPLL with sub-1μs locking time for a 2 GHz frequency hopping. A Digital Hop Control (DHC), based on a digital pre-distortion and a two-point modulation scheme, is exploited to compensate oscillator's non-linearity which allows the main loop to corre...

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Bibliographic Details
Main Authors: Grimaldi, Luigi, Iesurum, Agata, Boi, Giovanni, Versolatto, Fabio, Steffan, Giovanni, Padovan, Fabio, Koltsov, Heorhii, Bevilacqua, Andrea, Cherniak, Dmytro
Format: Conference Proceeding
Language:English
Subjects:
CMOS
Digital Phase-locked loops (DPLLs)
digital pre-distortion
digitally-controlled oscillator (DCO)
fast locking
Frequency modulation
frequency synthesizers
Jitter
mm-Wave
Phase modulation
Power demand
Prototypes
Spread spectrum communication
Time-frequency analysis
Transient analysis
Wireless communication
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Summary:This work presents a 48-58GHz DTC based FracN DPLL with sub-1μs locking time for a 2 GHz frequency hopping. A Digital Hop Control (DHC), based on a digital pre-distortion and a two-point modulation scheme, is exploited to compensate oscillator's non-linearity which allows the main loop to correct a smaller phase error, thus boosting the locking transient. The prototype has been fabricated in 28-nm CMOS technlogy, it achieves 137 fs inetgrated jitter in the 10 kHz -to25 MHz frequency range with 30 mW power consumption and worst in band frac-N spur level of -50.5 dBc (at 50 GHz). This design, working with a reference frequency of 100 MHz, achieves the best integrated jitter, FOMJ (-242.5 dB) and FOMN (-269.7 dB), among 30-60 GHzx fractional-N DPLLs.
ISSN:2643-1319
DOI:10.1109/ESSERC62670.2024.10719534