An MDAC-Less Pipelined ADC for AI-Powered Medical Imaging Applications

An imaging system generally trades between image quality and power consumption. The higher the pixel density, the better the quality of image, however, at the expense of power hungry front-end data converters. Recently, the intensive back-end computation has been tailored with the integration of art...

Full description

Saved in:
Bibliographic Details
Published in:IEEE sensors journal 2024-12, Vol.24 (23), p.39182-39194
Main Authors: Dhiman, Saurabh, Shrimali, Hitesh
Format: Article
Language:English
Subjects:
Algorithm
analog-to-digital converter (ADC)
Approximation algorithms
Artificial intelligence
Artificial neural networks
Biomedical imaging
capacitor mismatch
Capacitors
data converters
low power
medical imaging
monotonic switching
multiplying digital-to-analog converter (MDAC)
pipeline ADC
Pipelines
positron emission tomography (PET) imaging
Power demand
Sensors
Signal processing
Signal processing algorithms
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:An imaging system generally trades between image quality and power consumption. The higher the pixel density, the better the quality of image, however, at the expense of power hungry front-end data converters. Recently, the intensive back-end computation has been tailored with the integration of artificial intelligence (AI) algorithms in the image signal processing (ISP) unit. Such AI-powered ISP has dragged the front-end data converters to its limits. Sensing the need of low-power, hardware-efficient front-end data conversion, this work proposes the unrolled monotonic binary split algorithm (UMBSA)-based pipelined analog-to-digital converter (ADC) architecture for the AI-driven medical imaging applications. The proposed algorithm eliminates the need of m-bit/stage digital-to-analog converter (DAC) and the resulting capacitor mismatch, thereby providing an area- and energy-efficient solution to the on-chip AI-based imaging systems. A 40-MSa/s, 8-bit prototype ADC is designed and fabricated in CMOS 180-nm silicon-on-insulator (SOI) technology for medical imaging applications. The measurement results show a 55 fJ \cdot mm2/conv. step of figure-of-merit with 58.97 dBc of spurious-free dynamic range (SFDR) and 43.11 dB of signal-to-noise-and-distortion ratio (SNDR) at an input data rate of 3.22 MHz, respectively.
ISSN:1530-437X
1558-1748
DOI:10.1109/JSEN.2024.3477608