A Low-Noise Fractional- N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC

This work presents a digital-to-time converter (DTC)-based fractional- N phase-locked loop (PLL) achieving low jitter and low spurs. Thanks to the proposed resistor-based inverse-constant-slope (R-ICS) DTC, the DTC random jitter is drastically reduced while retaining the excellent linearity perform...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2024-12, p.1-13
Main Authors: Salvi, Pietro, Dartizio, Simone M., Rossoni, Michele, Tesolin, Francesco, Castoro, Giacomo, Lacaita, Andrea L., Levantino, Salvatore
Format: Article
Language:English
Subjects:
Bang-bang
Capacitors
digital phase-locked loop (PLL)
digital-to-time converter (DTC)
DTC range reduction
fractional spurs
Generators
inverse-constant-slope (ICS)
Jitter
least-mean-square (LMS)
Linearity
low-jitter PLL
Phase locked loops
Phase noise
Power demand
Resistors
Voltage
White noise
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Summary:This work presents a digital-to-time converter (DTC)-based fractional- N phase-locked loop (PLL) achieving low jitter and low spurs. Thanks to the proposed resistor-based inverse-constant-slope (R-ICS) DTC, the DTC random jitter is drastically reduced while retaining the excellent linearity performance of the conventional ICS-DTC architecture. Moreover, a tailored DTC range reduction technique is introduced to further improve DTC random noise. The PLL prototype has been fabricated in 28-nm CMOS and consumes 16.7 mW, with an active area of 0.21 mm 2 . It generates an output frequency in the 8.75-10.25-GHz range from a 125-MHz input reference frequency. At 9.25-GHz near-integer channels, it achieves a 67-fs rms jitter, a - 108.5-dBc/Hz in-band phase noise (at 10-kHz offset), and fractional spurs below - 63 dBc.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2024.3501196