Design-Agnostic Distributed Timing Fault Injection Monitor With End-to-End Design Automation

• Published in: IEEE journal of solid-state circuits 2024-12, p.1-12
• Main Authors: He, Yan, Su, Yumin, Yang, Kaiyuan
• Format: Article
• Language: English
• Subjects: Circuit faults; Clocks; Delay locked loop (DLL); Delays; design automation; fault injection attacks (FIAs); fault injection monitors; hardware security; Logic gates; Monitoring; Registers; Sensors; Temperature measurement; Temperature sensors; Voltage
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.2024.3504546

Fault injection attacks (FIAs) induce hardware failures in circuits and exploit these faults to compromise the security of the system. It has been demonstrated that FIAs can bypass system security mechanisms, cause faulty outputs, and gain access to secret information. Certain types of FIAs can be mounted with little effort by tampering with clock signals and/or the chip's operating conditions. To mitigate such low-cost, yet powerful attacks, we propose a fully synthesizable and distributable in situ fault injection monitor that employs a delay locked loop (DLL) to track the pulsewidth of the clock. We further develop a fully automated design framework to optimize and implement the FIA monitors at any process node. Our design is fabricated and verified in 65-nm CMOS technology with a small footprint of 1500 \mu m ^2 . It can lock to clock frequencies from 2 MHz to 1.26 GHz while detecting all 12 types of possible clock glitches, as well as timing FIA injections via the supply voltage, electromagnetic (EM) signals, and chip temperature.