A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting

• Published in: IEEE journal of solid-state circuits 2024-12, p.1-14
• Main Authors: Ye, Siyuan, Gao, Jihang, Li, Jie, Chen, Zhuoyi, Xu, Xinhang, Cui, Jiajia, Luan, Yaohui, Ye, Le, Zhang, Xing, Huang, Ru, Shen, Linxiao
• Format: Article
• Language: English
• Subjects: Analog-to-digital converter (ADC); Bandwidth; Capacitors; continuous-time SAR (CTSAR); correlated level shifting (CLS); Costs; detect-and-skip (DAS); Gain; Noise; open-then-close CLS (OCCLS); pipelined-SAR; Prototypes; Redundancy; ring amplifier (ring-amp); Switches; System-on-chip; Temperature measurement
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2024.3497175

This work presents a 2-mW 70.7-dB SNDR 200-MS/s pipelined-successive-approximation-register (SAR) analog-to-digital converter (ADC) with a continuous-time SAR-assisted detect-and-skip (CTDAS) and open-then-close correlated level shifting (OCCLS). In the first-stage SAR ADC, we propose using the continuous-time SAR (CTSAR) as the coarse SAR ADC in the detect-and-skip (DAS) scheme, thus parallelizing MSB conversion with ADC sampling. Furthermore, in the residue amplifier (RA), an OCCLS technique is proposed, which significantly speeds up the first correlated level shifting (CLS) phase by open-loop amplification and consequently enhances the equivalent open-loop gain at negligible extra time cost. An on-chip background self-detect-and-cut loop is used for the OCCLS to attain a PVT-robust high equivalent open-loop gain. For RA implementation, a hybrid static-floating ring-amp structure is adopted to improve the noise performance while fitting in well with the OCCLS scheme. Thanks to the proposed techniques, the 22-nm prototype achieves 70.7-dB SNDR under 200 MS/s while consuming only 2.0 mW from a 0.9-V supply. It measures 177.7-dB FoMs, which is the highest among ADCs with equivalent or higher sampling rates.