Enhancing AI Acceleration: A Calibration-Free, PVT-Robust Analog Compute-in-Memory Macro With Activation Functions

Most analog compute-in-memory (ACiM) works only focus on the multiple-accumulate (MAC) operation while neglecting the activation function (AF) in the digital domain. The frequent data conversion greatly reduces the benefits obtained by analog computing. This letter proposes an efficient 8-bit in-mem...

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Bibliographic Details
Published in:IEEE solid-state circuits letters 2025, Vol.8, p.9-12
Main Authors: Wang, Hechen, Liu, Renzhi, Dorrance, Richard, Dasalukunte, Deepak, Mylarappa Gowda, Niranjan, Carlton, Brent
Format: Article
Language:English
Subjects:
Accuracy
Analog computing
Artificial intelligence
artificial intelligence (AI)
Calibration
Capacitors
charge domain computing
CMOS
Computation
compute-in-memory (CiM)
Data conversion
In-memory computing
Ladders
machine learning (ML) accelerator
mixed-signal
multiply-accumulate (MAC) operation
neural networks (NNs)
PVT
Rails
Random access memory
Signal paths
static random-access memory (SRAM)
Switches
Throughput
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Summary:Most analog compute-in-memory (ACiM) works only focus on the multiple-accumulate (MAC) operation while neglecting the activation function (AF) in the digital domain. The frequent data conversion greatly reduces the benefits obtained by analog computing. This letter proposes an efficient 8-bit in-memory MAC with hybrid capacitor ladders. Then, a sparsity-aware R-2R DAC and an embedded SAR-ADC that reuses the capacitor ladders in the MAC are introduced to reduce the conversion overhead. Two on-chip AF schemes are included to further improve efficiency. Finally, differential signal path offers first-order PVT cancellation that improves computing accuracy and reduces the need for calibration.
ISSN:2573-9603
2573-9603
DOI:10.1109/LSSC.2024.3510679