Loading…
Machine Learning-based feasibility estimation of digital blocks in BCD technology
Analog-on-Top Mixed Signal (AMS) Integrated Circuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the placement of digital blocks. Specific features of the area, such as size and shape, have...
Saved in:
| Main Authors: | , , , , , , , |
|---|---|
| Format: | Conference Proceeding |
| Language: | English |
| Subjects: | |
| Online Access: | Request full text |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| cited_by | |
|---|---|
| cites | |
| container_end_page | 6 |
| container_issue | |
| container_start_page | 1 |
| container_title | |
| container_volume | |
| creator | Daghero, Francesco Faraone, Gabriele Grosso, Michelangelo Pagliari, Daniele Jahier Di Carolo, Nicola Franchino, Giovanna Antonella Licastro, Dario Serianni, Eugenio |
| description | Analog-on-Top Mixed Signal (AMS) Integrated Circuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the placement of digital blocks. Specific features of the area, such as size and shape, have a relevant impact on the possibility of implementing the digital logic with the required functionality. We present a Machine Learning (ML)-based evaluation methodology for predicting the feasibility of digital implementation using a set of high-level features. This approach aims to avoid time-consuming Place-and-Route trials, enabling rapid feedback between Digital and Analog Back-End designers during top-level placement. |
| doi_str_mv | 10.1109/DTTIS62212.2024.10780062 |
| format | conference_proceeding |
| fullrecord | <record><control><sourceid>ieee_CHZPO</sourceid><recordid>TN_cdi_ieee_primary_10780062</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10780062</ieee_id><sourcerecordid>10780062</sourcerecordid><originalsourceid>FETCH-LOGICAL-i712-fa1cb571c470c6a1aea9db230336f47755d253623a617c2c3a35474528d740b53</originalsourceid><addsrcrecordid>eNo1kEFOwzAQAA0SElXpDzj4Awnr3dhOjpACrVSEEDlwqzaO0xqCg-pc8nuQgNPcRqMRQirIlYLqZt0021eDqDBHwCJXYEsAg2diVdmqJA1kSGF5LhZYEmYl0tulWKX0DgCkKgCsFuLlid0xRC93nk8xxEPWcvKd7D2n0IYhTLP0aQqfPIUxyrGXXTiEiQfZDqP7SDJEeVev5eTdMY7DeJivxEXPQ_KrPy5F83Df1Jts9_y4rW93WbAKs56Va7VVrrDgDCv2XHUtEhCZvrBW6w41GSQ2yjp0xKQLW2gsO1tAq2kprn-1wXu__zr9FJ7m_f8E-gYZzFC1</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Machine Learning-based feasibility estimation of digital blocks in BCD technology</title><source>IEEE Xplore All Conference Series</source><creator>Daghero, Francesco ; Faraone, Gabriele ; Grosso, Michelangelo ; Pagliari, Daniele Jahier ; Di Carolo, Nicola ; Franchino, Giovanna Antonella ; Licastro, Dario ; Serianni, Eugenio</creator><creatorcontrib>Daghero, Francesco ; Faraone, Gabriele ; Grosso, Michelangelo ; Pagliari, Daniele Jahier ; Di Carolo, Nicola ; Franchino, Giovanna Antonella ; Licastro, Dario ; Serianni, Eugenio</creatorcontrib><description>Analog-on-Top Mixed Signal (AMS) Integrated Circuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the placement of digital blocks. Specific features of the area, such as size and shape, have a relevant impact on the possibility of implementing the digital logic with the required functionality. We present a Machine Learning (ML)-based evaluation methodology for predicting the feasibility of digital implementation using a set of high-level features. This approach aims to avoid time-consuming Place-and-Route trials, enabling rapid feedback between Digital and Analog Back-End designers during top-level placement.</description><identifier>EISSN: 2832-823X</identifier><identifier>EISBN: 9798350363128</identifier><identifier>DOI: 10.1109/DTTIS62212.2024.10780062</identifier><language>eng</language><publisher>IEEE</publisher><subject>analog-mixed-signal ; artificial intelligence ; Decision trees ; Design methodology ; EDA ; Integrated circuits ; layout ; Logic ; machine learning ; Manufacturing ; Maximum likelihood estimation ; Place and Route ; Predictive models ; Shape ; Silicon</subject><ispartof>IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (Online), 2024, p.1-6</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10780062$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,27906,54536,54913</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10780062$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Daghero, Francesco</creatorcontrib><creatorcontrib>Faraone, Gabriele</creatorcontrib><creatorcontrib>Grosso, Michelangelo</creatorcontrib><creatorcontrib>Pagliari, Daniele Jahier</creatorcontrib><creatorcontrib>Di Carolo, Nicola</creatorcontrib><creatorcontrib>Franchino, Giovanna Antonella</creatorcontrib><creatorcontrib>Licastro, Dario</creatorcontrib><creatorcontrib>Serianni, Eugenio</creatorcontrib><title>Machine Learning-based feasibility estimation of digital blocks in BCD technology</title><title>IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (Online)</title><addtitle>DTTIS</addtitle><description>Analog-on-Top Mixed Signal (AMS) Integrated Circuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the placement of digital blocks. Specific features of the area, such as size and shape, have a relevant impact on the possibility of implementing the digital logic with the required functionality. We present a Machine Learning (ML)-based evaluation methodology for predicting the feasibility of digital implementation using a set of high-level features. This approach aims to avoid time-consuming Place-and-Route trials, enabling rapid feedback between Digital and Analog Back-End designers during top-level placement.</description><subject>analog-mixed-signal</subject><subject>artificial intelligence</subject><subject>Decision trees</subject><subject>Design methodology</subject><subject>EDA</subject><subject>Integrated circuits</subject><subject>layout</subject><subject>Logic</subject><subject>machine learning</subject><subject>Manufacturing</subject><subject>Maximum likelihood estimation</subject><subject>Place and Route</subject><subject>Predictive models</subject><subject>Shape</subject><subject>Silicon</subject><issn>2832-823X</issn><isbn>9798350363128</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2024</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNo1kEFOwzAQAA0SElXpDzj4Awnr3dhOjpACrVSEEDlwqzaO0xqCg-pc8nuQgNPcRqMRQirIlYLqZt0021eDqDBHwCJXYEsAg2diVdmqJA1kSGF5LhZYEmYl0tulWKX0DgCkKgCsFuLlid0xRC93nk8xxEPWcvKd7D2n0IYhTLP0aQqfPIUxyrGXXTiEiQfZDqP7SDJEeVev5eTdMY7DeJivxEXPQ_KrPy5F83Df1Jts9_y4rW93WbAKs56Va7VVrrDgDCv2XHUtEhCZvrBW6w41GSQ2yjp0xKQLW2gsO1tAq2kprn-1wXu__zr9FJ7m_f8E-gYZzFC1</recordid><startdate>20241014</startdate><enddate>20241014</enddate><creator>Daghero, Francesco</creator><creator>Faraone, Gabriele</creator><creator>Grosso, Michelangelo</creator><creator>Pagliari, Daniele Jahier</creator><creator>Di Carolo, Nicola</creator><creator>Franchino, Giovanna Antonella</creator><creator>Licastro, Dario</creator><creator>Serianni, Eugenio</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20241014</creationdate><title>Machine Learning-based feasibility estimation of digital blocks in BCD technology</title><author>Daghero, Francesco ; Faraone, Gabriele ; Grosso, Michelangelo ; Pagliari, Daniele Jahier ; Di Carolo, Nicola ; Franchino, Giovanna Antonella ; Licastro, Dario ; Serianni, Eugenio</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i712-fa1cb571c470c6a1aea9db230336f47755d253623a617c2c3a35474528d740b53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2024</creationdate><topic>analog-mixed-signal</topic><topic>artificial intelligence</topic><topic>Decision trees</topic><topic>Design methodology</topic><topic>EDA</topic><topic>Integrated circuits</topic><topic>layout</topic><topic>Logic</topic><topic>machine learning</topic><topic>Manufacturing</topic><topic>Maximum likelihood estimation</topic><topic>Place and Route</topic><topic>Predictive models</topic><topic>Shape</topic><topic>Silicon</topic><toplevel>online_resources</toplevel><creatorcontrib>Daghero, Francesco</creatorcontrib><creatorcontrib>Faraone, Gabriele</creatorcontrib><creatorcontrib>Grosso, Michelangelo</creatorcontrib><creatorcontrib>Pagliari, Daniele Jahier</creatorcontrib><creatorcontrib>Di Carolo, Nicola</creatorcontrib><creatorcontrib>Franchino, Giovanna Antonella</creatorcontrib><creatorcontrib>Licastro, Dario</creatorcontrib><creatorcontrib>Serianni, Eugenio</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore / Electronic Library Online (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Daghero, Francesco</au><au>Faraone, Gabriele</au><au>Grosso, Michelangelo</au><au>Pagliari, Daniele Jahier</au><au>Di Carolo, Nicola</au><au>Franchino, Giovanna Antonella</au><au>Licastro, Dario</au><au>Serianni, Eugenio</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Machine Learning-based feasibility estimation of digital blocks in BCD technology</atitle><btitle>IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (Online)</btitle><stitle>DTTIS</stitle><date>2024-10-14</date><risdate>2024</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><eissn>2832-823X</eissn><eisbn>9798350363128</eisbn><abstract>Analog-on-Top Mixed Signal (AMS) Integrated Circuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the placement of digital blocks. Specific features of the area, such as size and shape, have a relevant impact on the possibility of implementing the digital logic with the required functionality. We present a Machine Learning (ML)-based evaluation methodology for predicting the feasibility of digital implementation using a set of high-level features. This approach aims to avoid time-consuming Place-and-Route trials, enabling rapid feedback between Digital and Analog Back-End designers during top-level placement.</abstract><pub>IEEE</pub><doi>10.1109/DTTIS62212.2024.10780062</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | EISSN: 2832-823X |
| ispartof | IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (Online), 2024, p.1-6 |
| issn | 2832-823X |
| language | eng |
| recordid | cdi_ieee_primary_10780062 |
| source | IEEE Xplore All Conference Series |
| subjects | analog-mixed-signal artificial intelligence Decision trees Design methodology EDA Integrated circuits layout Logic machine learning Manufacturing Maximum likelihood estimation Place and Route Predictive models Shape Silicon |
| title | Machine Learning-based feasibility estimation of digital blocks in BCD technology |
| url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T09%3A07%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_CHZPO&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Machine%20Learning-based%20feasibility%20estimation%20of%20digital%20blocks%20in%20BCD%20technology&rft.btitle=IEEE%20International%20Conference%20on%20Design%20&%20Test%20of%20Integrated%20Micro%20&%20Nano-Systems%20(Online)&rft.au=Daghero,%20Francesco&rft.date=2024-10-14&rft.spage=1&rft.epage=6&rft.pages=1-6&rft.eissn=2832-823X&rft_id=info:doi/10.1109/DTTIS62212.2024.10780062&rft.eisbn=9798350363128&rft_dat=%3Cieee_CHZPO%3E10780062%3C/ieee_CHZPO%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i712-fa1cb571c470c6a1aea9db230336f47755d253623a617c2c3a35474528d740b53%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=10780062&rfr_iscdi=true |