A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm ^ Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture

• Published in: IEEE journal of solid-state circuits 2024-12, p.1-8
• Main Authors: Haraguchi, Masaru, Fujino, Yorinobu, Yokoyama, Yoshisato, Chang, Ming-Hung, Hsu, Yu-Hao, Cheng, Hong-Chen, Nii, Koji, Wang, Yih, Chang, Tsung-Yung Jonathan
• Format: Article
• Language: English
• Subjects: 1W1R; 3-nm; Clocks; Delays; double-pumping; Generators; Loading; Microprocessors; Optimization; pseudo; Random access memory; Sensors; static random access memory (SRAM); Tracking loops; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2024.3509958

A double-pumped 1-read and 1-write pseudo-2-port 6T static random access memory (SRAM) with folded bitline (BL) multi-bank (MB) architecture is demonstrated on 3 nm FinFET technology. A new self-timed clock generator is proposed to optimize wordline (WL) negating with shortcut path circuit (WLNS). sense-amplifier-enable interlocking (SAEI) circuit and the clock generator can provide a 3.6% increase in the maximum operating frequency ( f_{\text{MAX}} ) by minimizing the tail period of the read operation. The data pre-loading write driver (PLWD) circuit facilitates a shorter separation time between read and write operations by overlapping BL pre-charge and write data loading on the BL, thereby leading to a 4.4% improvement in f_{\text{MAX}} . The WLNS and PLWD contribute to 2.4% f_{\text{MAX}} gain by promoting contention-free features between the BL pre-charge and write driver circuits. Furthermore, the real-time dynamic performance scaling (RTDPS) feature ensures a robust SRAM read/write operation across the entire supply voltage range by optimizing WL pulsewidth. The test chip measurement results show that it achieves a 5.9% increase in f_{\text{MAX}} at high voltage ranges. In addition, the memory density is 21.1 Mb/mm ^{2} , and f_{\text{MAX}} is 4.3 GHz, resulting in a figure of merit (FoM) of 90.7 GHz \times Mb/mm ^{2} /V.