SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor for IoT Devices

This article proposes a novel self-organizing map (SOM) hardware architecture based on computing-in-memory (CIM) for addressing high power consumption caused by frequent memory access. The proposed CIM macros process weight subtraction and neuron update in memory, reducing memory access during recal...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2024-12, p.1-15
Main Authors: Lu, Yuncheng, Zhang, Xin, Wang, Bo, Kim, Tony Tae-Hyoung
Format: Article
Language:English
Subjects:
Computer architecture
Computing-in-memory (CIM)
dead neuron pruning
Hardware
hardware accelerator
In-memory computing
Internet of Things
Internet of Things (IoT) devices
low power
Neurons
Parallel processing
Self-organizing feature maps
self-organizing map (SOM)
Throughput
Training
Vectors
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Summary:This article proposes a novel self-organizing map (SOM) hardware architecture based on computing-in-memory (CIM) for addressing high power consumption caused by frequent memory access. The proposed CIM macros process weight subtraction and neuron update in memory, reducing memory access during recall and learning stages by 50% and 80%, respectively. Besides, the neurons with extremely low update rates are pruned adaptively to avoid unnecessary signal toggling, saving power by up to 12.5%. The test chip fabricated in CMOS 65-nm technology achieves the peak power efficiency of 449.1 GCUPS/W and 556.5 GCPS/W during the learning and recall stages, respectively. Moreover, the chip-to-chip link (C2CL) for inter-chip communication improves the scalability of the system. Various applications, including data clustering, image quantization, and gesture recognition with different SOM neural network sizes, have been tested on the prototype chip successfully.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2024.3510877