Optimized Modular Adder Architecture for Cryptographic Applications on FPGAs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2024-12, p.1-1
• Main Authors: Bachir, Madani, Salah, Azzaz Mohamed, Said, Sadoudi, Redouane, Kaibou, da Silva, Bruno
• Format: Article
• Language: English
• Subjects: Adders; Arithmetic; Clocks; Computer architecture; Cryptography; Delays; Design automation; Field Programmable Gate Array (FPGA); Field programmable gate arrays; Finite field arithmetic; Galois fields; Modular adder; Ripple carry adder; Table lookup
• ISSN: 0278-0070
• DOI: 10.1109/TCAD.2024.3518412

Modular addition is a fundamental operation in public-key cryptographic algorithms operating in finite fields, such as Elliptic Curve Cryptography (ECC), Chebyshev polynomials and Post-Quantum Cryptography (PQC). The performance of these cryptographic algorithms is limited by the conventional modular adder approach, which incorporates two cascaded adders in series. This approach leads to a doubled critical path delay, ultimately causing a decrease in frequency despite utilizing a high-performance adder.This research presents a high-performance, low-area architecture for a modular adder, employing a novel approach.Specifically designed for various prime fields recommended in public key cryptography, the architecture optimally utilizes the carry chain and exploits the structural advantages of the 7-series FPGA and series beyond. Implementation results demonstrate superior performance, achieving operating frequencies of 290.0 MHz for 192 bits and 205.5 MHz for 1024 bits.Notably, the proposed design performs modular addition in a single clock cycle, resulting in an approximate 57% frequency enhancement compared to the conventional approach. Consequently, this architecture stands as an optimal solution for systems demanding high-speed operations.