Robust In-Memory Computation With Bayesian Analog Error Mitigating Codes

In-memory computation (IMC) is a promising technology for enabling low-latency and energy-efficient deep learning and artificial intelligence (AI) applications at edge devices. However, the IMC crossbar array, typically implemented using resistive random access memory (RRAM), faces hardware defects...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on signal processing 2025, Vol.73, p.534-548
Main Authors: Jha, Nilesh Kumar, Guo, Huayan, Lau, Vincent K. N.
Format: Article
Language:English
Subjects:
analog codes
Artificial intelligence
Bayes methods
Bayesian analysis
Bayesian signal processing
Central Processing Unit
Codes
Computation
Decoding
Errors
Forward error correction
In memory computation
Machine learning
Memory devices
Neural networks
Noise
Probabilistic models
Programming
Random access memory
Robustness (mathematics)
Sparse matrices
Statistical inference
Training
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In-memory computation (IMC) is a promising technology for enabling low-latency and energy-efficient deep learning and artificial intelligence (AI) applications at edge devices. However, the IMC crossbar array, typically implemented using resistive random access memory (RRAM), faces hardware defects that pose a significant challenge to reliable computation. This paper presents a robust IMC scheme utilizing Bayesian neural network-accelerated analog codes. Our approach includes a new datapath design comprising a parity matrix generator and a low-complexity decoder module to facilitate analog codes for IMC. Moreover, we introduce a Gaussian mixture model-based error prior to capture impulsive error statistics and leverage variational Bayesian inference (VBI) techniques for training neural network weights. Extensive simulations confirm the effectiveness of our proposed solution compared to various state-of-the-art baseline schemes.
ISSN:1053-587X
1941-0476
DOI:10.1109/TSP.2025.3530149