Architecture and design of a pseudo two-port VLSI snoopy cache memory

A CMOS VLSI cache memory subsystem that includes a 72 K-bit cache memory, an 11 K-bit tag memory, a 1.3 K-bit state array, two special buffers and cache control logic, has been designed and integrated on a microprocessor chip. The architecture, design and analysis of the cache design are presented....

Full description

Saved in:
Bibliographic Details
Main Authors: Chuang, S.C.-M., Bruss, A.
Format: Conference Proceeding
Language:English
Subjects:
Cache memory
Central Processing Unit
CMOS process
Delay
Logic arrays
Logic design
System buses
System performance
System-on-a-chip
Very large scale integration
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A CMOS VLSI cache memory subsystem that includes a 72 K-bit cache memory, an 11 K-bit tag memory, a 1.3 K-bit state array, two special buffers and cache control logic, has been designed and integrated on a microprocessor chip. The architecture, design and analysis of the cache design are presented. The design achieves higher system performance by reducing the cache reload penalty through a pseudo-two-port architecture which utilizes a reload buffer and a store-back buffer. It also maintains cache data coherency and supports multiprocessing by bus snooping. A single-port tag is used for concurrent snooping and CPU access with an enhanced write-once protocol. A cost-effective 'locked replacement' scheme was incorporated to maintain data coherency in these two special buffers. Cache modeling and analysis were carried out to derive the proper design point.< >
DOI:10.1109/CMPEUR.1990.113651