Signature Analysis of Dispatch Schemes in Wafer Fabrication

Signature analysis is used to characterize lot dispatch priority schemes in wafer fabrication, a complex manufacturing operation. A number of idealized dispatch schemes are evaluated using a comprehensive assessment criterion. The production system analyzed in this paper is large in comparison to pr...

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Bibliographic Details
Published in:IEEE transactions on components, hybrids, and manufacturing technology hybrids, and manufacturing technology, 1986-12, Vol.9 (4), p.518-525
Main Authors: Dayhoff, J., Atherton, R.
Format: Article
Language:English
Subjects:
Applied sciences
Electronics
Exact sciences and technology
Fabrication
Integrated circuit manufacture
Integrated circuit modeling
Integrated circuits
Job shop scheduling
Manufacturing processes
Operations research
Production facilities
Production systems
Semiconductor device modeling
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Semiconductor process modeling
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Summary:Signature analysis is used to characterize lot dispatch priority schemes in wafer fabrication, a complex manufacturing operation. A number of idealized dispatch schemes are evaluated using a comprehensive assessment criterion. The production system analyzed in this paper is large in comparison to previous studies on manufacturing scheduling. Real dispatch schemes depend strongly on the characteristics of human implementation. Signature analysis provides the basis for measuring organizational performance by comparing formal dispatch schemes with each other and with actual dispatch schemes used in wafer fabrication.
ISSN:0148-6411
1558-3082
DOI:10.1109/TCHMT.1986.1136660