Two hardware implementations for the Montgomery modular multiplication: sequential versus parallel

Modular multiplication is the most dominant part of the computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. This paper describes the characteristics of two architectures designed to implement modular multiplicatio...

Full description

Saved in:
Bibliographic Details
Main Authors: Nedjah, N., de Macedo Mourelle, L.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Computer architecture
Concurrent computing
Field programmable gate arrays
Hardware
Iterative algorithms
Prototypes
Public key
Public key cryptography
Systems engineering and theory
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by
cites
container_end_page 8
container_issue
container_start_page 3
container_title
container_volume
creator Nedjah, N.
de Macedo Mourelle, L.
description Modular multiplication is the most dominant part of the computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. This paper describes the characteristics of two architectures designed to implement modular multiplication using the fast Montgomery algorithm: the first FPGA prototype has an iterative sequential architecture while the second has a systolic array-based architecture. The paper compares both prototypes using the time/spl times/area classic factor.
doi_str_mv 10.1109/SBCCI.2002.1137629
format conference_proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1137629</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1137629</ieee_id><sourcerecordid>1137629</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-d6b579510079ff6c0b7d85df3e75238a9ca353ae6eec70afc873d3d8eb25e8703</originalsourceid><addsrcrecordid>eNotUFFLwzAYDIigzv0Bfckf2Ewb0iS-aVE3mPjgfB5fmy8ukjY1SR379xbdvRwHd8dxhNwUbFkUTN-9P9b1elkyVk6ay6rUZ-SKyUqLQjGpL8g8pS82gWvBFb8kzfYQ6B6iOUBE6rrBY4d9huxCn6gNkeY90tfQ58_QYTzSLpjRQ6Td6LMbvGv_rPc04fc4BR14-oMxjYkOEMF79Nfk3IJPOD_xjHw8P23r1WLz9rKuHzYLV0iRF6ZqhJx2smmntVXLGmmUMJajFCVXoFvgggNWiK1kYFslueFGYVMKVJLxGbn973WIuBui6yAed6cb-C-F4VaP</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Two hardware implementations for the Montgomery modular multiplication: sequential versus parallel</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Nedjah, N. ; de Macedo Mourelle, L.</creator><creatorcontrib>Nedjah, N. ; de Macedo Mourelle, L.</creatorcontrib><description>Modular multiplication is the most dominant part of the computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. This paper describes the characteristics of two architectures designed to implement modular multiplication using the fast Montgomery algorithm: the first FPGA prototype has an iterative sequential architecture while the second has a systolic array-based architecture. The paper compares both prototypes using the time/spl times/area classic factor.</description><identifier>ISBN: 0769518079</identifier><identifier>ISBN: 9780769518077</identifier><identifier>DOI: 10.1109/SBCCI.2002.1137629</identifier><language>eng</language><publisher>IEEE</publisher><subject>Algorithm design and analysis ; Computer architecture ; Concurrent computing ; Field programmable gate arrays ; Hardware ; Iterative algorithms ; Prototypes ; Public key ; Public key cryptography ; Systems engineering and theory</subject><ispartof>Proceedings. 15th Symposium on Integrated Circuits and Systems Design, 2002, p.3-8</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1137629$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1137629$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Nedjah, N.</creatorcontrib><creatorcontrib>de Macedo Mourelle, L.</creatorcontrib><title>Two hardware implementations for the Montgomery modular multiplication: sequential versus parallel</title><title>Proceedings. 15th Symposium on Integrated Circuits and Systems Design</title><addtitle>SBCCI</addtitle><description>Modular multiplication is the most dominant part of the computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. This paper describes the characteristics of two architectures designed to implement modular multiplication using the fast Montgomery algorithm: the first FPGA prototype has an iterative sequential architecture while the second has a systolic array-based architecture. The paper compares both prototypes using the time/spl times/area classic factor.</description><subject>Algorithm design and analysis</subject><subject>Computer architecture</subject><subject>Concurrent computing</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>Iterative algorithms</subject><subject>Prototypes</subject><subject>Public key</subject><subject>Public key cryptography</subject><subject>Systems engineering and theory</subject><isbn>0769518079</isbn><isbn>9780769518077</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2002</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotUFFLwzAYDIigzv0Bfckf2Ewb0iS-aVE3mPjgfB5fmy8ukjY1SR379xbdvRwHd8dxhNwUbFkUTN-9P9b1elkyVk6ay6rUZ-SKyUqLQjGpL8g8pS82gWvBFb8kzfYQ6B6iOUBE6rrBY4d9huxCn6gNkeY90tfQ58_QYTzSLpjRQ6Td6LMbvGv_rPc04fc4BR14-oMxjYkOEMF79Nfk3IJPOD_xjHw8P23r1WLz9rKuHzYLV0iRF6ZqhJx2smmntVXLGmmUMJajFCVXoFvgggNWiK1kYFslueFGYVMKVJLxGbn973WIuBui6yAed6cb-C-F4VaP</recordid><startdate>2002</startdate><enddate>2002</enddate><creator>Nedjah, N.</creator><creator>de Macedo Mourelle, L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2002</creationdate><title>Two hardware implementations for the Montgomery modular multiplication: sequential versus parallel</title><author>Nedjah, N. ; de Macedo Mourelle, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-d6b579510079ff6c0b7d85df3e75238a9ca353ae6eec70afc873d3d8eb25e8703</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Algorithm design and analysis</topic><topic>Computer architecture</topic><topic>Concurrent computing</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>Iterative algorithms</topic><topic>Prototypes</topic><topic>Public key</topic><topic>Public key cryptography</topic><topic>Systems engineering and theory</topic><toplevel>online_resources</toplevel><creatorcontrib>Nedjah, N.</creatorcontrib><creatorcontrib>de Macedo Mourelle, L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nedjah, N.</au><au>de Macedo Mourelle, L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Two hardware implementations for the Montgomery modular multiplication: sequential versus parallel</atitle><btitle>Proceedings. 15th Symposium on Integrated Circuits and Systems Design</btitle><stitle>SBCCI</stitle><date>2002</date><risdate>2002</risdate><spage>3</spage><epage>8</epage><pages>3-8</pages><isbn>0769518079</isbn><isbn>9780769518077</isbn><abstract>Modular multiplication is the most dominant part of the computation performed in public-key cryptography systems such as the RSA cryptosystem. The operation is time consuming for large operands. This paper describes the characteristics of two architectures designed to implement modular multiplication using the fast Montgomery algorithm: the first FPGA prototype has an iterative sequential architecture while the second has a systolic array-based architecture. The paper compares both prototypes using the time/spl times/area classic factor.</abstract><pub>IEEE</pub><doi>10.1109/SBCCI.2002.1137629</doi><tpages>6</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 0769518079
ispartof Proceedings. 15th Symposium on Integrated Circuits and Systems Design, 2002, p.3-8
issn
language eng
recordid cdi_ieee_primary_1137629
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Algorithm design and analysis
Computer architecture
Concurrent computing
Field programmable gate arrays
Hardware
Iterative algorithms
Prototypes
Public key
Public key cryptography
Systems engineering and theory
title Two hardware implementations for the Montgomery modular multiplication: sequential versus parallel
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T20%3A33%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Two%20hardware%20implementations%20for%20the%20Montgomery%20modular%20multiplication:%20sequential%20versus%20parallel&rft.btitle=Proceedings.%2015th%20Symposium%20on%20Integrated%20Circuits%20and%20Systems%20Design&rft.au=Nedjah,%20N.&rft.date=2002&rft.spage=3&rft.epage=8&rft.pages=3-8&rft.isbn=0769518079&rft.isbn_list=9780769518077&rft_id=info:doi/10.1109/SBCCI.2002.1137629&rft_dat=%3Cieee_6IE%3E1137629%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-d6b579510079ff6c0b7d85df3e75238a9ca353ae6eec70afc873d3d8eb25e8703%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1137629&rfr_iscdi=true