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MOVE: model verification system
The authors address the issue of model correctness in an automated model generating system for a CAD system. They have designed a verification system called the model verifier (MOVE) to solve this problem. This approach is based on observation that if there exists an error in the generated model, it...
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creator | Kang, S. Szygenda, S.A. |
description | The authors address the issue of model correctness in an automated model generating system for a CAD system. They have designed a verification system called the model verifier (MOVE) to solve this problem. This approach is based on observation that if there exists an error in the generated model, it is in the functional primitives or the signal interconnections. Therefore, to verify the model, functional correctness checking for primitives and connection correctness checking for interconnections between primitives are used. The reason for the use of two distinct approaches in functional checking is to verify the models efficiently by overcoming the limitations of two approaches and using some heuristics. The advantage of this method is that it can efficiently verify the models and can be used in a practical sense.< > |
doi_str_mv | 10.1109/PCCC.1991.113891 |
format | conference_proceeding |
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They have designed a verification system called the model verifier (MOVE) to solve this problem. This approach is based on observation that if there exists an error in the generated model, it is in the functional primitives or the signal interconnections. Therefore, to verify the model, functional correctness checking for primitives and connection correctness checking for interconnections between primitives are used. The reason for the use of two distinct approaches in functional checking is to verify the models efficiently by overcoming the limitations of two approaches and using some heuristics. The advantage of this method is that it can efficiently verify the models and can be used in a practical sense.< ></description><identifier>ISBN: 0818621338</identifier><identifier>ISBN: 9780818621338</identifier><identifier>DOI: 10.1109/PCCC.1991.113891</identifier><language>eng</language><publisher>IEEE Comput. Soc. Press</publisher><subject>Automatic logic units ; Automatic programming ; Buildings ; Circuit simulation ; Design automation ; Digital systems ; Logic design ; Logic devices ; Prototypes ; Signal generators</subject><ispartof>[1991 Proceedings] Tenth Annual International Phoenix Conference on Computers and Communications, 1991, p.762-768</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/113891$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,4035,4036,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/113891$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kang, S.</creatorcontrib><creatorcontrib>Szygenda, S.A.</creatorcontrib><title>MOVE: model verification system</title><title>[1991 Proceedings] Tenth Annual International Phoenix Conference on Computers and Communications</title><addtitle>PCCC</addtitle><description>The authors address the issue of model correctness in an automated model generating system for a CAD system. They have designed a verification system called the model verifier (MOVE) to solve this problem. This approach is based on observation that if there exists an error in the generated model, it is in the functional primitives or the signal interconnections. Therefore, to verify the model, functional correctness checking for primitives and connection correctness checking for interconnections between primitives are used. The reason for the use of two distinct approaches in functional checking is to verify the models efficiently by overcoming the limitations of two approaches and using some heuristics. The advantage of this method is that it can efficiently verify the models and can be used in a practical sense.< ></description><subject>Automatic logic units</subject><subject>Automatic programming</subject><subject>Buildings</subject><subject>Circuit simulation</subject><subject>Design automation</subject><subject>Digital systems</subject><subject>Logic design</subject><subject>Logic devices</subject><subject>Prototypes</subject><subject>Signal generators</subject><isbn>0818621338</isbn><isbn>9780818621338</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1991</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj0tLAzEURgMiVGv3xY3zB6bm5jFz405CfUClLmy35U5yI5GOlckg9N9bqN_mcDYHPiHmIBcA0t2_e-8X4BycVKODC3EtEbBRoDVOxKyUL3maMdY06krcva23y4eqP0TeV7885JQDjfnwXZVjGbm_EZeJ9oVn_5yKzdPyw7_Uq_Xzq39c1Z9KwVgblpqYrIkIMiWnrE5djBQi2gZlkC6lzjqKNsTWWKCujdRYityikxj0VNyeu5mZdz9D7mk47s4X9B9EEDub</recordid><startdate>1991</startdate><enddate>1991</enddate><creator>Kang, S.</creator><creator>Szygenda, S.A.</creator><general>IEEE Comput. Soc. Press</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1991</creationdate><title>MOVE: model verification system</title><author>Kang, S. ; Szygenda, S.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-g221t-4e03aea54d810ff9253fbddacd85680c09ffb59ad5cd7451ab7da65ade78908c3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1991</creationdate><topic>Automatic logic units</topic><topic>Automatic programming</topic><topic>Buildings</topic><topic>Circuit simulation</topic><topic>Design automation</topic><topic>Digital systems</topic><topic>Logic design</topic><topic>Logic devices</topic><topic>Prototypes</topic><topic>Signal generators</topic><toplevel>online_resources</toplevel><creatorcontrib>Kang, S.</creatorcontrib><creatorcontrib>Szygenda, S.A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kang, S.</au><au>Szygenda, S.A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>MOVE: model verification system</atitle><btitle>[1991 Proceedings] Tenth Annual International Phoenix Conference on Computers and Communications</btitle><stitle>PCCC</stitle><date>1991</date><risdate>1991</risdate><spage>762</spage><epage>768</epage><pages>762-768</pages><isbn>0818621338</isbn><isbn>9780818621338</isbn><abstract>The authors address the issue of model correctness in an automated model generating system for a CAD system. They have designed a verification system called the model verifier (MOVE) to solve this problem. This approach is based on observation that if there exists an error in the generated model, it is in the functional primitives or the signal interconnections. Therefore, to verify the model, functional correctness checking for primitives and connection correctness checking for interconnections between primitives are used. The reason for the use of two distinct approaches in functional checking is to verify the models efficiently by overcoming the limitations of two approaches and using some heuristics. The advantage of this method is that it can efficiently verify the models and can be used in a practical sense.< ></abstract><pub>IEEE Comput. Soc. Press</pub><doi>10.1109/PCCC.1991.113891</doi><tpages>7</tpages></addata></record> |
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identifier | ISBN: 0818621338 |
ispartof | [1991 Proceedings] Tenth Annual International Phoenix Conference on Computers and Communications, 1991, p.762-768 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Automatic logic units Automatic programming Buildings Circuit simulation Design automation Digital systems Logic design Logic devices Prototypes Signal generators |
title | MOVE: model verification system |
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