Effect of static power dissipation in burn-in environment on yield of VLSI

The leakage power is expected to increase with scaling of CMOS technology. The increased leakage is a strong function of the elevated temperature and voltage stress. As a consequence; under the burn-in (BI) conditions the elevated leakage power may cause increased post burn-in fallout. In this paper...

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Bibliographic Details
Main Authors: Vassighi, A., Semenov, O., Sachdev, M., Keshavarzi, A.
Format: Conference Proceeding
Language:English
Subjects:
Bismuth
Circuit testing
CMOS technology
Immune system
Power dissipation
Stress
Temperature distribution
Thermal resistance
Very large scale integration
Voltage
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Summary:The leakage power is expected to increase with scaling of CMOS technology. The increased leakage is a strong function of the elevated temperature and voltage stress. As a consequence; under the burn-in (BI) conditions the elevated leakage power may cause increased post burn-in fallout. In this paper the impact of elevated leakage and technology scaling in burn-in environment on post BI yield is analyzed. We have also shown that to maintain a constant post-BI yield loss, the burn-in temperature should go down by 10/spl deg/C for each technology generation. We also show that at static burn-in conditions, the die temperature is increased exponentially and range of optimal stressed voltage and temperature for fixed post burn-in yield loss is reduced significantly, when CMOS technology is aggressively scaled down.
ISSN:1550-5774
2377-7966
DOI:10.1109/DFTVS.2002.1173497