A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator

A clock and data recovery (CDR) circuit with a novel two-mode phase comparator is proposed. The 10-Gb/s CDR integrated circuit (IC) operates both for consecutive identical digits (CID) and data transition density variations. This advance is achieved through the use of our novel two-mode phase compar...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 2003-02, Vol.38 (2), p.192-197
Main Authors: Nosaka, H., Ishii, K., Enoki, T., Shibata, T.
Format: Article
Language:English
Subjects:
Bang-bang control
Circuits
Clocks
Comparators
Data mining
Data recovery
Density
Integrated circuits
Jitter
Phase locked loops
Photonics
Pulse circuits
Sampling methods
Switches
Tolerances
Voltage
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A clock and data recovery (CDR) circuit with a novel two-mode phase comparator is proposed. The 10-Gb/s CDR integrated circuit (IC) operates both for consecutive identical digits (CID) and data transition density variations. This advance is achieved through the use of our novel two-mode phase comparator, which enables us to determine an optimal phase-locked loop parameter for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 pspp for a 2/sup 7/-1 pseudorandom bit sequence with up to 1024 CIDs. The results also show that the jitter transfer and jitter tolerance are unaffected by data transition density factors of between 1/8 and 1/2.
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2002.807408