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Mass-productive ultra-low temperature ALD SiO/sub 2/ process promising for sub-90 nm memory and logic devices

For the first time, ultra-low temperature ALD SiO/sub 2/ is successfully developed and applied on W/WN/poly-Si stack gates as a dual spacer for the enhancement of data retention time. ALD SiO/sub 2/ deposition is performed at 75/spl deg/C using HCD and H/sub 2/O as precursors and pyridine as a catal...

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Main Authors: Jae-Eun Park, Ja-Hum Ku, Joo-Won Lee, Jong-ho Yang, Kang-Soo Chu, Seung-Hwan Lee, Moon-Han Park, Nae-In Lee, Ho-Kyu Kang, Kwang-Pyuk Suh, Byoung-Ha Cho, Byoung-Chul Kim, Cheol-Ho Shin
Format: Conference Proceeding
Language:English
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Summary:For the first time, ultra-low temperature ALD SiO/sub 2/ is successfully developed and applied on W/WN/poly-Si stack gates as a dual spacer for the enhancement of data retention time. ALD SiO/sub 2/ deposition is performed at 75/spl deg/C using HCD and H/sub 2/O as precursors and pyridine as a catalyst. Using the ALD SiO/sub 2/ process, SiO/sub 2/ layers are deposited on W/WN/poly-Si stack gates without W oxidation. The gate resistances of the W/WN/poly-Si stack gates do not exhibit any difference between SiN single spacer and SiO/sub 2//SiN dual spacer schemes, which indicates that W oxidation does not occur during the ALD SiO/sub 2/ deposition for dual spacer formation. Conclusively, the significant improvement (>50%) of data retention time is achieved by employing SiO/sub 2//SiN dual spacers at W/WN/poly-Si stack gates in a 130 nm DRAM device. In addition, excellent short channel characteristics of Vth are identified by applying a low temperature ALD SiO/sub 2/ layer as a dual spacer on sub-100 nm SRAM devices.
DOI:10.1109/IEDM.2002.1175819