Optimization of 1.8V I/O circuits for performance, reliability at the 100 nm technology node

We describe the methodology and challenges in designing robust receiver and driver buffers in a state-of-the-art sub-100 nm CMOS technology. Issues addressed are the gate voltage limitations due to very thin gate oxides, channel hot carriers, process variability and design margins. The bi-directiona...

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Bibliographic Details
Main Authors: Menezes, V., Keshav, C.B., Gupta, S., Roopashree, M., Krishnan, S., Amerasekera, A., Palau, G.
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
CMOS logic circuits
CMOS process
CMOS technology
Degradation
Hot carriers
Impedance
Instruments
Logic devices
Voltage
Online Access:Request full text
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Description
Summary:We describe the methodology and challenges in designing robust receiver and driver buffers in a state-of-the-art sub-100 nm CMOS technology. Issues addressed are the gate voltage limitations due to very thin gate oxides, channel hot carriers, process variability and design margins. The bi-directional buffer is 90 /spl mu/m/spl times/114 /spl mu/m in size and has a maximum speed of 150 MHz with a 50 ohm termination.
ISSN:1063-9667
2380-6923
DOI:10.1109/ICVD.2003.1183125