Trace-driven rapid pipeline architecture evaluation scheme for ASIP design

This paper proposes a rapid evaluation scheme of pipeline architectures using phase-accurate simulation with only delay model and trace. With latency information for every stage, we can decide if an instruction in one stage can proceed to the next stage or if an instruction can be issued for each cy...

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Bibliographic Details
Main Authors: Jun Kyoung Kim, Tag Gon Kim
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Application specific processors
Delay
Embedded system
Emulation
Hardware
Modeling
Pipelines
Registers
Time to market
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Description
Summary:This paper proposes a rapid evaluation scheme of pipeline architectures using phase-accurate simulation with only delay model and trace. With latency information for every stage, we can decide if an instruction in one stage can proceed to the next stage or if an instruction can be issued for each cycle without evaluating the value for registers. Branch target becomes available with trace generated by fast instruction set simulation. Fast verification time becomes possible because instruction set simulation is performed only once.
DOI:10.1109/ASPDAC.2003.1195005