A highly efficient AES cipher chip

We present an efficient hardware implementation of the AES (advanced encryption standard) algorithm, with key expansion capability. Instead of the widely used table-lookup implementation of the S-box, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64% and i...

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Bibliographic Details
Main Authors: Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu
Format: Conference Proceeding
Language:English
Subjects:
Application specific integrated circuits
Clocks
CMOS technology
Cryptography
Data security
Field programmable gate arrays
Hardware
NIST
Random access memory
Throughput
Online Access:Request full text
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Summary:We present an efficient hardware implementation of the AES (advanced encryption standard) algorithm, with key expansion capability. Instead of the widely used table-lookup implementation of the S-box, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64% and is easily pipelined to achieve high throughput rate. Using a typical 0.25 /spl mu/m CMOS technology, the throughput rate is 2.977 Gbps for 128 bit keys, 2.510 Gbps for 192 bit keys, and 2.169 Gbps for 256 bit keys, with a 250 MHz clock. Testability of the design is also considered. The area of the core circuit is about 1,279/spl times/1,271 /spl mu/m/sup 2/.
DOI:10.1109/ASPDAC.2003.1195078