A high-speed clockless serial link transceiver

We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high off-chip data rates by using multiplexing transmitters and demultiplexing receivers that interface parallel on-chip data paths with high-speed,...

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Bibliographic Details
Main Authors: Teifel, J., Manohar, R.
Format: Conference Proceeding
Language:English
Subjects:
Circuits
Clocks
CMOS technology
Communication system control
Demultiplexing
Synchronization
Synchronous generators
Transceivers
Transmitters
Very large scale integration
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Summary:We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high off-chip data rates by using multiplexing transmitters and demultiplexing receivers that interface parallel on-chip data paths with high-speed, serial off-chip buses. While synchronous transceivers commonly use multi-phase clocks to control the data multiplexing and demultiplexing, our clockless transceiver uses a token-ring architecture that eliminates complex clock generation and synchronization circuitry. Furthermore, our clockless receiver dynamically self-adjusts its sampling rate to match the bit rate of the transmitter. Our SPICE simulations report that in a 0.18-/spl mu/m CMOS technology this transceiver design operates at up to 3-Gb/s and dissipates 77 mW of power with a 1.8-V supply voltage.
ISSN:1522-8681
DOI:10.1109/ASYNC.2003.1199175