Loading…
Petri net based interface analysis for fast IP-core integration
An interface process generation methodology, based on Petri nets, is described for fast integrating point-to-point communicating modules. Formal basis of this methodology ease behavioral property-checking and consistent execution of the generated interface process. The exposed technique allows fast...
Saved in:
Main Authors: | , , |
---|---|
Format: | Conference Proceeding |
Language: | English |
Subjects: | |
Online Access: | Request full text |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
cited_by | |
---|---|
cites | |
container_end_page | 42 |
container_issue | |
container_start_page | 34 |
container_title | |
container_volume | |
creator | de Oliveira Filho, J.A. de Lima, M.E. Maciel, P.R. |
description | An interface process generation methodology, based on Petri nets, is described for fast integrating point-to-point communicating modules. Formal basis of this methodology ease behavioral property-checking and consistent execution of the generated interface process. The exposed technique allows fast incorporation of third-party cores into SoPC systems design where integration task is often a barrier for reusability. |
doi_str_mv | 10.1109/MEMCOD.2003.1210084 |
format | conference_proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_1210084</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1210084</ieee_id><sourcerecordid>1210084</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-f3853d9f68a6a5812b479bdac01fa95d10f23f218267c84461db106276802133</originalsourceid><addsrcrecordid>eNotj81KAzEURgMiKHWeoJu8wIz35j8rkbFqoaVddF_uzCQSqVNJsunbK9pvczaHAx9jS4QOEfzjdrXtdy-dAJAdCgRw6oY13jqwxmv0Qqo71pTyCb9TSksN9-xpH2pOfA6VD1TCxNNcQ440Bk4znS4lFR7PmUcqla_37XjO4c_5yFTTeX5gt5FOJTRXLtjhdXXo39vN7m3dP2_ahFbXNkqn5eSjcWRIOxSDsn6YaASM5PWEEIWMAp0wdnRKGZwGBCOscSBQygVb_mdTCOH4ndMX5cvx-lL-AAqRRrE</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Petri net based interface analysis for fast IP-core integration</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>de Oliveira Filho, J.A. ; de Lima, M.E. ; Maciel, P.R.</creator><creatorcontrib>de Oliveira Filho, J.A. ; de Lima, M.E. ; Maciel, P.R.</creatorcontrib><description>An interface process generation methodology, based on Petri nets, is described for fast integrating point-to-point communicating modules. Formal basis of this methodology ease behavioral property-checking and consistent execution of the generated interface process. The exposed technique allows fast incorporation of third-party cores into SoPC systems design where integration task is often a barrier for reusability.</description><identifier>ISBN: 9780769519234</identifier><identifier>ISBN: 0769519237</identifier><identifier>DOI: 10.1109/MEMCOD.2003.1210084</identifier><language>eng</language><publisher>IEEE</publisher><subject>Assembly systems ; Consumer electronics ; Delay ; Digital systems ; Hardware ; Informatics ; Petri nets ; Process design ; Software systems ; Time to market</subject><ispartof>First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings, 2003, p.34-42</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1210084$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1210084$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>de Oliveira Filho, J.A.</creatorcontrib><creatorcontrib>de Lima, M.E.</creatorcontrib><creatorcontrib>Maciel, P.R.</creatorcontrib><title>Petri net based interface analysis for fast IP-core integration</title><title>First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings</title><addtitle>MEMCOD</addtitle><description>An interface process generation methodology, based on Petri nets, is described for fast integrating point-to-point communicating modules. Formal basis of this methodology ease behavioral property-checking and consistent execution of the generated interface process. The exposed technique allows fast incorporation of third-party cores into SoPC systems design where integration task is often a barrier for reusability.</description><subject>Assembly systems</subject><subject>Consumer electronics</subject><subject>Delay</subject><subject>Digital systems</subject><subject>Hardware</subject><subject>Informatics</subject><subject>Petri nets</subject><subject>Process design</subject><subject>Software systems</subject><subject>Time to market</subject><isbn>9780769519234</isbn><isbn>0769519237</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotj81KAzEURgMiKHWeoJu8wIz35j8rkbFqoaVddF_uzCQSqVNJsunbK9pvczaHAx9jS4QOEfzjdrXtdy-dAJAdCgRw6oY13jqwxmv0Qqo71pTyCb9TSksN9-xpH2pOfA6VD1TCxNNcQ440Bk4znS4lFR7PmUcqla_37XjO4c_5yFTTeX5gt5FOJTRXLtjhdXXo39vN7m3dP2_ahFbXNkqn5eSjcWRIOxSDsn6YaASM5PWEEIWMAp0wdnRKGZwGBCOscSBQygVb_mdTCOH4ndMX5cvx-lL-AAqRRrE</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>de Oliveira Filho, J.A.</creator><creator>de Lima, M.E.</creator><creator>Maciel, P.R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2003</creationdate><title>Petri net based interface analysis for fast IP-core integration</title><author>de Oliveira Filho, J.A. ; de Lima, M.E. ; Maciel, P.R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-f3853d9f68a6a5812b479bdac01fa95d10f23f218267c84461db106276802133</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Assembly systems</topic><topic>Consumer electronics</topic><topic>Delay</topic><topic>Digital systems</topic><topic>Hardware</topic><topic>Informatics</topic><topic>Petri nets</topic><topic>Process design</topic><topic>Software systems</topic><topic>Time to market</topic><toplevel>online_resources</toplevel><creatorcontrib>de Oliveira Filho, J.A.</creatorcontrib><creatorcontrib>de Lima, M.E.</creatorcontrib><creatorcontrib>Maciel, P.R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE/IET Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>de Oliveira Filho, J.A.</au><au>de Lima, M.E.</au><au>Maciel, P.R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Petri net based interface analysis for fast IP-core integration</atitle><btitle>First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings</btitle><stitle>MEMCOD</stitle><date>2003</date><risdate>2003</risdate><spage>34</spage><epage>42</epage><pages>34-42</pages><isbn>9780769519234</isbn><isbn>0769519237</isbn><abstract>An interface process generation methodology, based on Petri nets, is described for fast integrating point-to-point communicating modules. Formal basis of this methodology ease behavioral property-checking and consistent execution of the generated interface process. The exposed technique allows fast incorporation of third-party cores into SoPC systems design where integration task is often a barrier for reusability.</abstract><pub>IEEE</pub><doi>10.1109/MEMCOD.2003.1210084</doi><tpages>9</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISBN: 9780769519234 |
ispartof | First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings, 2003, p.34-42 |
issn | |
language | eng |
recordid | cdi_ieee_primary_1210084 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Assembly systems Consumer electronics Delay Digital systems Hardware Informatics Petri nets Process design Software systems Time to market |
title | Petri net based interface analysis for fast IP-core integration |
url | http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T10%3A26%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Petri%20net%20based%20interface%20analysis%20for%20fast%20IP-core%20integration&rft.btitle=First%20ACM%20and%20IEEE%20International%20Conference%20on%20Formal%20Methods%20and%20Models%20for%20Co-Design,%202003.%20MEMOCODE%20'03.%20Proceedings&rft.au=de%20Oliveira%20Filho,%20J.A.&rft.date=2003&rft.spage=34&rft.epage=42&rft.pages=34-42&rft.isbn=9780769519234&rft.isbn_list=0769519237&rft_id=info:doi/10.1109/MEMCOD.2003.1210084&rft_dat=%3Cieee_6IE%3E1210084%3C/ieee_6IE%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-i175t-f3853d9f68a6a5812b479bdac01fa95d10f23f218267c84461db106276802133%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=1210084&rfr_iscdi=true |