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A merged structure of LNA & sub-harmonic mixer for multi-band DCR applications
A merged structure of variable gain LNA and sub-harmonic mixer is designed for multi-band direct conversion receiver (DCR) applications with a 0.18 /spl mu/m CMOS process. The circuit uses inductive peaking loads to increase the 3dB-bandwidth and achieves 22.7/spl sim/32dB conversion gain, 2.8/spl s...
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| container_end_page | 246 vol.1 |
| container_issue | |
| container_start_page | 243 |
| container_title | |
| container_volume | 1 |
| creator | Kwang-Jin Koh Mun-Yang Park Yong-Sik Youn Scon-Ho Han Jang-Hong Choi Cheon-Soo Kim Sung-Do Kim Hyun-Kyu Yu |
| description | A merged structure of variable gain LNA and sub-harmonic mixer is designed for multi-band direct conversion receiver (DCR) applications with a 0.18 /spl mu/m CMOS process. The circuit uses inductive peaking loads to increase the 3dB-bandwidth and achieves 22.7/spl sim/32dB conversion gain, 2.8/spl sim/4.1dB DSB NF, -10.5/spl sim/4.1dBm IIP3 and 5/spl sim/17.3 dBm IIP2 from a 800 MHz to 2.4 GHz input range. The variable gain range is 11.5 dB at 2.1 GHz and typical LO to RF isolation is less than -50 dBm, and DC offset voltage is less than 10 mV. The overall power consumption is 17 mW with a 1.8 V supply voltage and the chip size is 2.3 mm/spl times/1.2 mm. |
| doi_str_mv | 10.1109/MWSYM.2003.1210925 |
| format | conference_proceeding |
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The circuit uses inductive peaking loads to increase the 3dB-bandwidth and achieves 22.7/spl sim/32dB conversion gain, 2.8/spl sim/4.1dB DSB NF, -10.5/spl sim/4.1dBm IIP3 and 5/spl sim/17.3 dBm IIP2 from a 800 MHz to 2.4 GHz input range. The variable gain range is 11.5 dB at 2.1 GHz and typical LO to RF isolation is less than -50 dBm, and DC offset voltage is less than 10 mV. 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The overall power consumption is 17 mW with a 1.8 V supply voltage and the chip size is 2.3 mm/spl times/1.2 mm.</description><subject>Application specific integrated circuits</subject><subject>Circuit noise</subject><subject>CMOS integrated circuits</subject><subject>Gain</subject><subject>Noise measurement</subject><subject>Parasitic capacitance</subject><subject>Radio frequency</subject><subject>Switches</subject><subject>Transceivers</subject><subject>Voltage</subject><issn>0149-645X</issn><issn>2576-7216</issn><isbn>9780780376953</isbn><isbn>0780376951</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotkMlKA0EURQsHMMb8gG5q5a7aV3PXMsQ4QEfBAXUVqtOvtKSHUN0N-vcGDBy4cBZ3cQg555BxDu5q9fb8scoEgMy42AmhD8hEaGuYFdwckpmzOeyQ1jgtj8gEuHLMKP1-Qk77_hsAdM7NhDzMaYPpEyvaD2ncDGNC2gVa7Pwl7ceSffnUdG3c0Cb-YKKhS7QZ6yGy0rcVvV48Ub_d1nHjh9i1_Rk5Dr7ucbbfKXm9Wb4s7ljxeHu_mBcscisHZhwvAwAG44LSruIyN84hoBRO59Yq5wIvUXGUQXlZ6byESmoQYEvrtZBTcvH_GxFxvU2x8el3vU8h_wBlX07u</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Kwang-Jin Koh</creator><creator>Mun-Yang Park</creator><creator>Yong-Sik Youn</creator><creator>Scon-Ho Han</creator><creator>Jang-Hong Choi</creator><creator>Cheon-Soo Kim</creator><creator>Sung-Do Kim</creator><creator>Hyun-Kyu Yu</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2003</creationdate><title>A merged structure of LNA & sub-harmonic mixer for multi-band DCR applications</title><author>Kwang-Jin Koh ; Mun-Yang Park ; Yong-Sik Youn ; Scon-Ho Han ; Jang-Hong Choi ; Cheon-Soo Kim ; Sung-Do Kim ; Hyun-Kyu Yu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i173t-691bf00ef69f459d138699e0e3295877499f1be41e3f4a3d58b0d350207b7a523</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Application specific integrated circuits</topic><topic>Circuit noise</topic><topic>CMOS integrated circuits</topic><topic>Gain</topic><topic>Noise measurement</topic><topic>Parasitic capacitance</topic><topic>Radio frequency</topic><topic>Switches</topic><topic>Transceivers</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Kwang-Jin Koh</creatorcontrib><creatorcontrib>Mun-Yang Park</creatorcontrib><creatorcontrib>Yong-Sik Youn</creatorcontrib><creatorcontrib>Scon-Ho Han</creatorcontrib><creatorcontrib>Jang-Hong Choi</creatorcontrib><creatorcontrib>Cheon-Soo Kim</creatorcontrib><creatorcontrib>Sung-Do Kim</creatorcontrib><creatorcontrib>Hyun-Kyu Yu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEL</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kwang-Jin Koh</au><au>Mun-Yang Park</au><au>Yong-Sik Youn</au><au>Scon-Ho Han</au><au>Jang-Hong Choi</au><au>Cheon-Soo Kim</au><au>Sung-Do Kim</au><au>Hyun-Kyu Yu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A merged structure of LNA & sub-harmonic mixer for multi-band DCR applications</atitle><btitle>IEEE MTT-S International Microwave Symposium Digest, 2003</btitle><stitle>MWSYM</stitle><date>2003</date><risdate>2003</risdate><volume>1</volume><spage>243</spage><epage>246 vol.1</epage><pages>243-246 vol.1</pages><issn>0149-645X</issn><eissn>2576-7216</eissn><isbn>9780780376953</isbn><isbn>0780376951</isbn><abstract>A merged structure of variable gain LNA and sub-harmonic mixer is designed for multi-band direct conversion receiver (DCR) applications with a 0.18 /spl mu/m CMOS process. The circuit uses inductive peaking loads to increase the 3dB-bandwidth and achieves 22.7/spl sim/32dB conversion gain, 2.8/spl sim/4.1dB DSB NF, -10.5/spl sim/4.1dBm IIP3 and 5/spl sim/17.3 dBm IIP2 from a 800 MHz to 2.4 GHz input range. The variable gain range is 11.5 dB at 2.1 GHz and typical LO to RF isolation is less than -50 dBm, and DC offset voltage is less than 10 mV. The overall power consumption is 17 mW with a 1.8 V supply voltage and the chip size is 2.3 mm/spl times/1.2 mm.</abstract><pub>IEEE</pub><doi>10.1109/MWSYM.2003.1210925</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0149-645X |
| ispartof | IEEE MTT-S International Microwave Symposium Digest, 2003, 2003, Vol.1, p.243-246 vol.1 |
| issn | 0149-645X 2576-7216 |
| language | eng |
| recordid | cdi_ieee_primary_1210925 |
| source | IEEE Xplore All Conference Series |
| subjects | Application specific integrated circuits Circuit noise CMOS integrated circuits Gain Noise measurement Parasitic capacitance Radio frequency Switches Transceivers Voltage |
| title | A merged structure of LNA & sub-harmonic mixer for multi-band DCR applications |
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