Ultra low power 6T-SRAM chip with improved transistor performance and reliability by HfO/sub 2/-Al/sub 2/O/sub 3/ high-K gate dielectric process optimization

Ultra low power CMOS 6T-SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric were successfully demonstrated (bit-cell size=2.14 /spl mu/m/sup 2/). Equivalent oxide thickness (EOT) of 1.56 nm, the thin high-k gate dielectric NMOS and PMOS transistor had 470 and 150 /spl mu/A//spl mu/...

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Main Authors: Chang-Bong Oh, Hyuk-Ju Ryu, Hee-Sung Kang, Myoung-Hwan Oh, Jong-Ho Lee, Nae-In Lee, Hyun-Woo Lee, Cheol-Hee Jun, Young-Wug Kim, Kwang-Pyuk Suh
Format: Conference Proceeding
Language:English
Subjects:
1f noise
Annealing
Hafnium oxide
High K dielectric materials
High-K gate dielectrics
Human computer interaction
Laminates
MOS devices
MOSFETs
Temperature
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Summary:Ultra low power CMOS 6T-SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric were successfully demonstrated (bit-cell size=2.14 /spl mu/m/sup 2/). Equivalent oxide thickness (EOT) of 1.56 nm, the thin high-k gate dielectric NMOS and PMOS transistor had 470 and 150 /spl mu/A//spl mu/m at Ioff=0.1 nA//spl mu/m and Vdd=1.2 V, respectively. By deliberate optimizing the conditions of post nitridation and post deposition annealing (PDA) such as O/sub 2/ and N/sub 2/ PDA temperature, 60 and 82% of NMOS and PMOS mobility, respectively, compared to those of oxynitride were achieved without increasing EOT. And also, reliabilities of TDDB and HCI, and flicker noise characteristics of the thin high-k transistors were improved. For the 6T-SRAM with optimized thin high-k gate dielectric, static noise margin (SNM), cell delay, and chip yield were comparable to those of the oxynitride device while dynamic power was more than 2 orders lower (Vdd=1.0/spl sim/1.2 V).
DOI:10.1109/VLSIT.2003.1221091