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A Fin-type independent-double-gate NFET
We present, to our knowledge, the first published experimental integration of two independent gates on a FinFET. The devices have symmetric gate oxide physical thicknesses of 8.5 nm, gate lengths ranging from 0.25 /spl mu/m to 5 /spl mu/m, and designed fin thicknesses ranging from 10 nm to 100 nm. I...
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creator | Fried, D.M. Nowak, E.J. Kedzierski, J. Duster, J.S. Komegay, K.T. |
description | We present, to our knowledge, the first published experimental integration of two independent gates on a FinFET. The devices have symmetric gate oxide physical thicknesses of 8.5 nm, gate lengths ranging from 0.25 /spl mu/m to 5 /spl mu/m, and designed fin thicknesses ranging from 10 nm to 100 nm. Independent-gate operation is demonstrated by modulating saturated drain current with both front and back gate voltages. |
doi_str_mv | 10.1109/DRC.2003.1226864 |
format | conference_proceeding |
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The devices have symmetric gate oxide physical thicknesses of 8.5 nm, gate lengths ranging from 0.25 /spl mu/m to 5 /spl mu/m, and designed fin thicknesses ranging from 10 nm to 100 nm. Independent-gate operation is demonstrated by modulating saturated drain current with both front and back gate voltages.</description><identifier>ISBN: 9780780377271</identifier><identifier>ISBN: 0780377273</identifier><identifier>DOI: 10.1109/DRC.2003.1226864</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuits ; CMOS technology ; Dielectrics ; Double-gate FETs ; Electrodes ; Etching ; FinFETs ; Lithography ; Plasma applications ; Silicon</subject><ispartof>61st Device Research Conference. Conference Digest (Cat. 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Independent-gate operation is demonstrated by modulating saturated drain current with both front and back gate voltages.</description><subject>Circuits</subject><subject>CMOS technology</subject><subject>Dielectrics</subject><subject>Double-gate FETs</subject><subject>Electrodes</subject><subject>Etching</subject><subject>FinFETs</subject><subject>Lithography</subject><subject>Plasma applications</subject><subject>Silicon</subject><isbn>9780780377271</isbn><isbn>0780377273</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2003</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><recordid>eNotT01LAzEUDIhQqXsXetmbp6wvedl8HMtqVSgtSO8l2bxIpK5Ldz303xuwwzADw-MNw9iDgEYIcE_PH10jAbARUmqr1Q2rnLFQiMZIIxasmqYvKFAtOiPu2OO63uSBz5eR6jxEGqnIMPP48xtOxD_9TPVu83K4Z7fJnyaqrr5kh5J2b3y7f33v1lueHcwcWzBaoUpoS4VUPpC1IrRGok1aCmmgp96Dc1JEwqB8TKkPpGM5bRXhkq3-32YiOo7n_O3Pl-N1Df4BVko9Yw</recordid><startdate>2003</startdate><enddate>2003</enddate><creator>Fried, D.M.</creator><creator>Nowak, E.J.</creator><creator>Kedzierski, J.</creator><creator>Duster, J.S.</creator><creator>Komegay, K.T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2003</creationdate><title>A Fin-type independent-double-gate NFET</title><author>Fried, D.M. ; Nowak, E.J. ; Kedzierski, J. ; Duster, J.S. ; Komegay, K.T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-35076434f3800424abe881b57238f621270ceca09921de3b4adffcbe6d4ab54e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2003</creationdate><topic>Circuits</topic><topic>CMOS technology</topic><topic>Dielectrics</topic><topic>Double-gate FETs</topic><topic>Electrodes</topic><topic>Etching</topic><topic>FinFETs</topic><topic>Lithography</topic><topic>Plasma applications</topic><topic>Silicon</topic><toplevel>online_resources</toplevel><creatorcontrib>Fried, D.M.</creatorcontrib><creatorcontrib>Nowak, E.J.</creatorcontrib><creatorcontrib>Kedzierski, J.</creatorcontrib><creatorcontrib>Duster, J.S.</creatorcontrib><creatorcontrib>Komegay, K.T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Fried, D.M.</au><au>Nowak, E.J.</au><au>Kedzierski, J.</au><au>Duster, J.S.</au><au>Komegay, K.T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A Fin-type independent-double-gate NFET</atitle><btitle>61st Device Research Conference. Conference Digest (Cat. No.03TH8663)</btitle><stitle>DRC</stitle><date>2003</date><risdate>2003</risdate><spage>45</spage><epage>46</epage><pages>45-46</pages><isbn>9780780377271</isbn><isbn>0780377273</isbn><abstract>We present, to our knowledge, the first published experimental integration of two independent gates on a FinFET. The devices have symmetric gate oxide physical thicknesses of 8.5 nm, gate lengths ranging from 0.25 /spl mu/m to 5 /spl mu/m, and designed fin thicknesses ranging from 10 nm to 100 nm. Independent-gate operation is demonstrated by modulating saturated drain current with both front and back gate voltages.</abstract><pub>IEEE</pub><doi>10.1109/DRC.2003.1226864</doi><tpages>2</tpages></addata></record> |
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ispartof | 61st Device Research Conference. Conference Digest (Cat. No.03TH8663), 2003, p.45-46 |
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language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Circuits CMOS technology Dielectrics Double-gate FETs Electrodes Etching FinFETs Lithography Plasma applications Silicon |
title | A Fin-type independent-double-gate NFET |
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