Realistic single-electron transistor modeling and novel CMOS/SET hybrid circuits

A practical single electron transistor (SET) model has been proposed with appropriate modifications to the previous analytical model. We have observed that non-ideal SET current behaviors such as turn-off and peak-to-valley ratio (PVCR) degradation is successfully reproduced by the new SET model. Ba...

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Bibliographic Details
Main Authors: Ki-Whan Song, Gwanghyeon Baek, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Dong-Soo Woo, Jae Sung Sim, Jong Duk Lee, Byung-Gook Park
Format: Conference Proceeding
Language:English
Subjects:
Analytical models
Circuit stability
Degradation
MOSFET circuits
Quantum dots
Semiconductor device modeling
Single electron transistors
Temperature control
Temperature distribution
Threshold voltage
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Summary:A practical single electron transistor (SET) model has been proposed with appropriate modifications to the previous analytical model. We have observed that non-ideal SET current behaviors such as turn-off and peak-to-valley ratio (PVCR) degradation is successfully reproduced by the new SET model. Based on the realistic SET model, we have developed a novel circuit scheme which enhances the stability of CMOS/SET hybrid logic. It is demonstrated that a universal literal gate with complementary self-biasing scheme operates quite well at high temperature in which the peak-to-valley current ratio of Coulomb oscillation degrades severely.
DOI:10.1109/NANO.2003.1231729