A high performance SSL IPSEC protocol aware security processor

A 64M transistor security macro processor enables 40k full SSL handshakes per second with 1024 b RSA. The 3DES, AES, ARC4, SHA-1, MD5 and modular exponentiation cryptographic primitives are also supported. The processor is fabricated in a 0.13 /spl mu/m 8M CMOS process and consumes 12 W at 500 MHz.

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Bibliographic Details
Main Authors: Carlson, D., Brasili, D., Hughes, A., Jain, A., Kiszely, T., Kodandapani, P., Vardharajan, A., Xanthopoulos, T., Yalala, V.
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Bandwidth
Cryptographic protocols
Cryptography
Delay
Engines
Entropy
Hardware
Random number generation
Registers
Online Access:Request full text
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Description
Summary:A 64M transistor security macro processor enables 40k full SSL handshakes per second with 1024 b RSA. The 3DES, AES, ARC4, SHA-1, MD5 and modular exponentiation cryptographic primitives are also supported. The processor is fabricated in a 0.13 /spl mu/m 8M CMOS process and consumes 12 W at 500 MHz.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2003.1234240