A wire-delay scalable microprocessor architecture for high performance systems

This scalable processor architecture consists of chained ALUs to minimize the physical distance between dependent instructions, thus mitigating the effect of long on-chip wire delays. Simulation studies demonstrate 1.3-15/spl times/ more instructions per clock than conventional superscalar architect...

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Bibliographic Details
Main Authors: Keckler, S.W., Burger, D., Moore, C.R., Nagarajan, R., Sankaralingam, K., Agarwal, V., Hrishikesh, M.S., Ranganathan, N., Shivakumar, P.
Format: Conference Proceeding
Language:English
Subjects:
Clocks
Computer architecture
Concurrent computing
Delay
Energy consumption
Microprocessors
Pipelines
Pulse inverters
Registers
Wire
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Description
Summary:This scalable processor architecture consists of chained ALUs to minimize the physical distance between dependent instructions, thus mitigating the effect of long on-chip wire delays. Simulation studies demonstrate 1.3-15/spl times/ more instructions per clock than conventional superscalar architectures.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2003.1234252